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TMS320F28379D: CLA and C28x Analog Read

ENES TASTEKIN
Prodigy 120 points

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

Hello, I am using the CLA unit for the control system in my project. I have set up the PWM in an up-down counting mode at a frequency of 100kHz (10us) to trigger both the PWM interrupt and the start of conversion (SOC) of the ADC unit.

Currently, the SOC of the ADC is triggered when the PWM counter is at zero, and each ADC conversion takes 2.5us to complete. PWM ISR2 is triggered when the PWM counter reaches its period value (5us), and PWM ISR triggers the CLA unit.

Now, I have set up both a 100kHz PWM interrupt and a 100kHz CLA unit in the main CPU.

I have a few questions regarding this situation:

  1. When the PWM counter reaches its period value and triggers the PWM interrupt, which in turn triggers the CLA unit, do these two units start compiling their code simultaneously, or is there a delay in the interrupt within the PWM ISR? Can I understand this?

  2. Should I reset the PWM ISR flag within the PWM interrupt or within the CLA unit?

  3. For the control system operations I want to perform in the CLA unit, I need specific ADC readings. However, these readings are also needed for calculations in the main CPU section. Do I need separate channels to read the ADC values for both the CLA unit and the CPU unit, or can I use the ADC data read by the CLA unit in the main CPU, and vice versa? Can both units read from the same memory simultaneously? Is there a risk of conflict?

  4. If I obtain a result with certain calculations within the PWM interrupt, how does transferring this result to the CLA unit affect my system? For example, if I send the sinusoidal signal obtained from PLL calculations in the PWM ISR function to the CLA unit, how does it affect my operations? Can the result from PLL be immediately written to the CLA unit? How does the parallel operation feature of CLA and CPU work here? Or should I perform the PLL operation within the CLA unit as well?

  • 0
    TI__Mastermind 22480 points

    Hello,

    From the CLA perspective, let me know if my understanding is correct:

    You are trying to use a PWM event both to trigger a PWM interrupt as well as trigger a task to start on the CLA. You are using the EPWMx_INT as a trigger source for your CLA task, correct? If this is the case, I would not recommend this set up as it would be difficult to synchronize the two operations.

    If my above understanding of your setup is correct, here are the answers to your questions:

    ENES TASTEKIN said:
    When the PWM counter reaches its period value and triggers the PWM interrupt, which in turn triggers the CLA unit, do these two units start compiling their code simultaneously, or is there a delay in the interrupt within the PWM ISR? Can I understand this?

    When the PWM counter reaches its period value it will trigger both the PWM interrupt and the CLA task simultaneously. On the c28x, the PWM ISR will be branched to and executed. On the CLA, the task will start executing. These will happen at the same time on each core, there should be no delay. The CLA task can be thought of as a separate interrupt that gets triggered by the same signal, it doesn't have any relation to the PWM interrupt itself.

    ENES TASTEKIN said:
    Should I reset the PWM ISR flag within the PWM interrupt or within the CLA unit?

    This would be the issue, you should technically reset this at the end of whichever interrupt/task finishes executing last, which you would have no way of knowing. For this reason, I would instead recommend one of the following options:

    • Software triggering the CLA task at the end of PWM ISR rather than using the PWM source as the trigger for the CLA. Then, you can clear the PWM ISR flag at the end of the CLA task since you know this is executing last. I believe you would also want to clear the interrupt ACK for the PWM ISR in the CLA task in this case as well. It would basically be an extension of the PWM ISR that gets executed on the CLA.
    • Have some flags in the c28x/CLA shared memory to synchronize these operations. You could have one flag that is set when the interrupt is finished and another for when the CLA task is finished, and then check these at the end of both the interrupt and the task to make sure only the last one to finish clears PWM ISR flag.
    ENES TASTEKIN said:
    For the control system operations I want to perform in the CLA unit, I need specific ADC readings. However, these readings are also needed for calculations in the main CPU section. Do I need separate channels to read the ADC values for both the CLA unit and the CPU unit, or can I use the ADC data read by the CLA unit in the main CPU, and vice versa? Can both units read from the same memory simultaneously? Is there a risk of conflict?

    You should not need to use separate channels of the ADC for this. For the ADC result register, both cores can access this memory simultaneously, so you should have no problem there. For all other peripheral registers that both the CPU and CLA have access to, there are arbitration rules that come into play (see the TRM section CLA and CPU Arbitration).

    ENES TASTEKIN said:
    If I obtain a result with certain calculations within the PWM interrupt, how does transferring this result to the CLA unit affect my system? For example, if I send the sinusoidal signal obtained from PLL calculations in the PWM ISR function to the CLA unit, how does it affect my operations? Can the result from PLL be immediately written to the CLA unit? How does the parallel operation feature of CLA and CPU work here? Or should I perform the PLL operation within the CLA unit as well?

    This is why you would want them to be synchronized in some way. You should not need to perform the computations in both, you can again use some sort of flag in the shared memory to indicate when the new PLL calculation is ready to be used by the CLA. On the CLA side it could poll this flag until it gets set and then read the data written in the CPU-to-CLA msg RAM or shared RAM.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 120 points

    it says that I can access the ADC results simultaneously in this section of the data sheet.

  • 0 in reply to ENES TASTEKIN
    TI__Mastermind 22480 points

    Thank you for pointing this out, I will modify my original response accordingly.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 120 points

    "Hello, in the tidm_1000 example, the CLA unit is triggered by the PWM interrupt, but the PWM ISR function code is left as a comment. When this function is used, both the IFR and PIACK bits are cleared, but within the CLA unit, only the PWM IFR bit is cleared with EPWM_clearEventTriggerInterruptFlag(base);. Now, in this usage, why isn't the PIACK bit cleared in the CLA unit with Interrupt_clearACKGroup(pie_group_no);? In which situations should we clear this bit?"

    Best Regards,

    Enes

  • 0 in reply to ENES TASTEKIN
    TI__Mastermind 22480 points

    Hi Enes,

    I will look into this and get back to you.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Mastermind 22480 points

    Hi Enes,

    Can you point me to which files and lines in the reference design you are asking about?

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 120 points

    Hi Delaney,

    there is in this section "C:\ti\C2000Ware_DigitalPower_SDK_4_03_01_00\solutions\tidm_1000\f2837x"

    1.vienna_clatask.cla > VIENNA_pfcControlCode();

    there is in this section, the pwm interrupt bit is reset (FIR), but the group bit is not reset (PIACK)

    2."vienna_main.c "also, the pwm interrupt function is included in the comment line in this section, can we use the pwm interrupt source without making  this definition?

    Best Regards,

    Enes

  • 0 in reply to ENES TASTEKIN
    TI__Mastermind 22480 points

    Hi Enes,

    I am looking into this with the reference design owner and will have a response back to you in the next couple of days. For now, I would recommend implementing the ISR and CLA task the same way as the reference design does. If I find that there is something specific about the reference design that would make these configurations different from your case, I will let you know.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Mastermind 22480 points

    Hi Enes,

    Sorry for the late response. 

    In the TIDA 1000 reference design, the ISR functionality can either be run from the main CPU (if VIENNA_CONTROL_RUNNING_ON == C28x_CORE) or this functionality can be offloaded to a CLA task (if VIENNA_CONTROL_RUNNING_ON == CLA_CORE). In both cases, the trigger is the PWM flag, which is why it should be cleared at the end in both implementations.

    One important distinction to make here is that when the code is running on the CLA core, the PWM interrupt itself is not triggering the CLA task. Rather, the same flag that would normally be used to trigger a PWM interrupt in the PIE is now instead being used to trigger a CLA task which can be thought of as a CLA "interrupt". The ACK bit gets set when an interrupt is triggered in the PIE and an ISR is branched to. In order to receive further interrupts after the initial interrupt, this bit needs to be cleared in the ISR. In the case of a CLA task, no interrupt is generated in the PIE and therefore the ACK is never set, which is why the task doesn't need to clear it.

    Best Regards,

    Delaney