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TMS320F280039C: Possible for ISR to occur between start and address for I2C controller?

Part Number: TMS320F280039C

Dear Champs,

I am asking this for our customer.

The user is migrating codes from one of our competitors onto F280039C and hopes the behavior to be the same as possible.

The user wonders

1) Is it possible to generate an I2C ISR between start and address when F280039C I2C controller is used?

Then, inside this I2C ISR, the user write I2C target address, then it outputs.

So far, from our example, it seems the user has to write I2C target address initially before an I2C ISR and then output S and address+R/W together and then an I2C ISR like TXRDY occurs. 

2) Being I2C controller, what are the occurrence timing of ISR for XRDY, ARDY event?

Is it possible to show a timing diagram like the above for the user to understand in more detail?