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TMS320F28P650DH: CPU1 and CPU2's code update

Jordan Zhou
Genius 10150 points
Part Number: TMS320F28P650DH


Hi,

F28P65 CPU1 and CPU2's code, can they be updated from CPU1 at one time?

F28P65 5 flash banks. 3 are for CPU1 while the other two for CPU2. Can the CPU1 erase and write the 5 flash banks at one time, to do the CPU1 and CPU2's code update?

Another doubt about ADC sampling capacitor Ch. In the datasheet, it's 14.5pF. Is this a fixed value? My point of view is: yes.

Thanks a lot.

Br, Jordan

  • +1
    TI__Genius 11081 points
    Jordan Zhou said:
    F28P65 CPU1 and CPU2's code, can they be updated from CPU1 at one time?

    Yes.

    Jordan Zhou said:
    F28P65 5 flash banks. 3 are for CPU1 while the other two for CPU2. Can the CPU1 erase and write the 5 flash banks at one time, to do the CPU1 and CPU2's code update?

    CPU1 has access to erase/program all flash banks in the device. In terms of simultaneous operation, only one flash bank can be programmed at a time. Other banks can be read at the same time (supports CPU1 and CPU2 simultaneously reading different banks while program or erase is ongoing for a third bank).

    Jordan Zhou said:
    Another doubt about ADC sampling capacitor Ch. In the datasheet, it's 14.5pF. Is this a fixed value? My point of view is: yes.

    This value is for the internal sampling capacitor model. It is fixed for 12bit mode (in 16bit mode, the model value is 32.5pF). The provided model is intended for use in evaluating your input circuit to determine sampling time requirements.

    Best regards,
    Ibukun