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TMS320F28035: Comparator issue

Part Number: TMS320F28035
Other Parts Discussed in Thread: C2000WARE

HI experts,

My customer has trouble using the f2803x's comparator for overvoltage protection. The trigger route is (comp2A vs DAC) -> DCBH -> DCBEVT1 -> one-shot latch.  

When they use hysteresis, the TZ can be triggered at the correct voltage level. However, once it's triggered, the voltage at the comp input pin has a 200mV step-up.

When not using hysteresis, the TZ is triggered all the time. Clearing the one-shot flag has no effect. The COMPSTS is 0, but DCBEVT1 is still triggered (Same when inverting the COMPOUT polarity).

Is the voltage step-up normal? Way DCBEVT still triggers when COMPSTS is 0?

Regards,

Hang.

  • Hi,

    Is the voltage step-up normal?

    The voltage step-up is normal, if the input signal is being driven with some high output impedance circuit.

    DCBEVT1 has to be manually cleared. Has the customer done this? 

    Best Regards,

    Ben Collier

  • Hi Ben,

    Thanks for answering, so the step-up is expected.

    DCBEVT1 has to be manually cleared. Has the customer done this? 

    Setting the clear bit of DCBEVT1 has no effect.

    Regards,

    Hang.

  • Hang,

    Please give me a couple days to try this myself.

    Best Regards,

    Ben Collier

  • Hi Ben,

    Is there any update on this?

    Thanks,

    Hang.

  • I'm sorry about the delays, I've been very busy and it takes some time to put a setup together to test something like this. I should have time tomorrow.

    Best Regards,

    Ben Collier

  • Hang,

    I am using our epwm_dcevent_trip_comp example that is located in [C2000WARE]/device_support/f2803x/examples/c28/epwm_dcevent_trip_comp. I am able to clear the trip zone flags by writing to the TZCLR register as long as DCBL, DCBH, DCAL, and DCAH are not actively setting the trip zone flags. Hysteresis being enabled or disabled has no effect on this. 

    The settings that control how the comparator output will affect DCAEVT1/2 and DCBEVT1/2 events can be found in the DCTRIPSEL and TZDCSEL registers. 

    From DCTRIPSEL register in this example: 

    DCBL -> TZ2

    DCBH -> COMP1OUT

    DCAL -> TZ2

    DCAH -> COMP1OUT

    From TZDCSEL register in this example: 

    DCBEVT2 -> disabled

    DCBEVT1 -> triggered when DCBH is low, do not care about DCBL

    DCAEVT2 -> disabled

    DCAEVT1 -> triggered when DCAH is low, do not care about DCAL

    With the above settings, the trip zone flags are set when COMPSTS is 0 and thus they can only be cleared when COMPSTS is 1. Please see the above snippet from the TRM to understand why they can only be cleared when the DC trip event is not present. Please have your customer try the example mentioned above and compare with their setup. Please let me know if they have trouble with this. 

    Best Regards,

    Ben Collier

  • Hi Ben,

    Thanks for reproducing the issue. In your configurations DCBEVT1 is triggered when DCBH is low, therefore the trip zone flag can be cleared when COMPSTS is 1.

    However, as I confirmed with customer, they are using TZDCSEL.ECAEVT1 = 2 & TZDCSEL.ECAEVT1 = 2 configuration. The flag should be set when COMPSTS is 1 and can be cleared when COMPSTS is 0, however, they can not clear the flag when COMPSTS is 0.

    As you said, enabling/disabling hysteresis should not affect the flag setting/clearing, but we observed that enabling hysteresis alone would cause the issue, even with rest of the configuration untouched.

    Regards,

    Hang.

     

  • Hang,

    Can the customer try replicating my above results with our example?