Part Number: TMS320F2809
Dear Champs,
I am asking this for our customer.
This is an extension project with an old design on F2809, and new FW guys are picking the old design and modifying a little bit.
For ADC, the user uses dual sequencer mode,
CONT_RUN=0
MAX_CONV1=7
The user wonders if they don't reset sequencer in the end of ADC ISR below,
AdcRegs.ADCTRL2.bit.RST_SEQ1=1;
can SEQ1 wrap around to CONV00 again after SEQ1 ends at CONV7 and then gets triggered even with CONT_RUN=0?
They are asking this because they find it does not matter if they remove AdcRegs.ADCTRL2.bit.RST_SEQ1=1; in the end of ADC ISR.
Therefore, they want us to confirm this.
