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F28069 I/O glitch

AAH
Prodigy 220 points

It is mentioned in sec3.4  SPRS698B that  GPIO19, GPIO34, GPIO35, GPIO36, GPIO37 and GPIO38 pins could glitch during power up if on chip VREG is used. Now, GPIO34 and GPIO37 are also used for boot mode selection. Will boot mode selection be affected in any way during power up, if on chip VREG is used?

In my case GPIO19 is the chip select pin for an E2PROM. Should I shift chip select to another pin?

  • 0
    TI__Guru 62975 points

    Amar,

    The glitch should only occur during the supply ramp.  The GPIO pins are read during boot-ROM execution which takes place well after the supply ramp is complete so it should not affect the F28069 boot selection.  You can refer to the Power-on Reset figure in the Power Sequencing section of the datasheet.

    -Tommy