TMS320F28388D: About IPC communication CPU1 to CM

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Hello Mr. expert,
when I examined the ipc c2000ware sample codes IPC_sendCommand(IPC_CPU1_L_CM_R, IPC_FLAG0, IPC_ADDR_CORRECTION_ENABLE, IPC_CMD_READ_MEM, (uint32_t)readData, 10); When I examine the function code, I see such a definition IPC_ADDR_CORRECTION_ENABLE, I searched for its meaning but I could not find anything, can you explain what IPC_ADDR_CORRECTION_ENABLE means?

  • Hi,

    I recommend that you look inside of the IPC_sendCommand() and IPC_readCommand() functions in ipc.c: 

    In above IPC_sendCommand(), address correction will adjust the address passed as an argument (assumed to be pointing to IPC_MsgRAM_LtoR) so that it is only an offset from the starting address of IPC_MsgRAM_LtoR.

    In IPC_readCommand(), address correction will add back the offset for the IPC Message RAM. 

    This feature exists due to the different addressing formats between the C28X core and the CM core, where each address represents a 16-bit word for C28X while each address represents 8-bit byte for arm core. Additionally, the memory mapped location of the MSG Ram may be different for different CPUs.

    If the address correction feature is not used for both send and receive commands, you must manually account for the above. 

    Best Regards,

    Ben Collier