Part Number: TMS320F2800157-Q1
Tool/software:
After the IIC communication sends valid data, a STOP bit is notgenerated, but a START bit is generated again. What is thereason?
The IIC configuration is derived from official routines
This is not necessary, sometimes the STOP bit is successfullygenerated and sometimes it is not
Hi Ming,
Is the I2C generating a repeated START condition (I2CMDR.BB = 1 and I2CMDR.STT = 1)? This mode is specifically relevant when the controller is configured as transmitter. In this mode, the I2C controller puts out a start condition at the end of each data type until it is finished transmitting based on the number of data bits in the BC field of I2CMDR. Refer to this chart for when STOP conditions are generated:
Best Regards,
Aishwarya
The BC bit of the MDR register configured by the IIC is 0, thatis, 8 bits of data. As you can see from the picture, all the datahas been sent and an ACK has been received, and a STOP bitshould be generated next, but a START is generated instead.This is not the first time I operate EEPROM, this error occurswhen I quickly read and write EEPRM process, after thisphenomenon, the IIC will hang, can not operate EEPROM.MCU reset to restore normal. In the Debug mode, the status ofrelated registers is as follows. For details, see the followingtwo figures.
Ming,
This is not the first time I operate EEPROM, this error occurswhen I quickly read and write EEPRM process,
This is probably the issue here. Even if the bus is 400 kHz, it is important to account for the time it takes to write anything. According to the AT24C256C Datasheet, a write cycle max time is 5ms. Whether you are writing a byte or a page, it can take up to 5 ms, so I would try adding a delay between reading/writing and after writing data. This is the code to refer to in the EEPROM interrupt example.
Best Regards,
Aishwarya
Hi,
You see my post about the IIC configuration, I have configured adelay of 5ms, using this delay functionDEVICE DELAY US(5000); Then I found that the problem maybe in the configuration of the IICMDR register. When I changedthe configuration to assign a one-time value to the MDR registeras shown in the figure, the probability of error will be muchsmaller. Can you help me explain the reason?
