Tool/software:
Hello,
could you help me with my issue. I use both cores of processor in my application. On CPU1 is generated signal, which is sent to CPU2 by means of Interprocessor comunication. And in CPU2 is done fourier analysis of generated signal by means of FFT libraries. Program in CPU1 and CPU2 is loaded from FLASH. The program on CPU2 works fine when size variables of structure RFFT_F32_STRUCT rfft is RFFT_SIZE = 256. The program on CPU2 doesn't work and is stuck in function Device_init(), when size variables of structure RFFT_F32_STRUCT rfft is RFFT_SIZE = 512.
I add cmd file of CPU2 program.
--define RFFT_ALIGNMENT=256
#if !defined(RFFT_ALIGNMENT)
#error define RFFT_ALIGNMENT under C2000 Linker -> Advanced Options -> Command File Preprocessing -> --define
#endif
MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000123, length = 0x0002DD
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0_4 : origin = 0x008000, length = 0x002800
//RAMGS14_15 : origin = 0x01A000, length = 0x001FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RESET : origin = 0x3FFFC0, length = 0x000002
/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASH : origin = 0x082000, length = 0x03BFF0 /* on-chip Flash */
// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
PAGE 1 :
BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD1 : origin = 0x00B800, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
//RAMGS0_2 : origin = 0x00C000, length = 0x003000
RAMGS11_15 : origin = 0x017000, length = 0x005000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASH PAGE = 0, ALIGN(8)
.text : > FLASH PAGE = 0, ALIGN(8)
codestart : > BEGIN PAGE = 0, ALIGN(8)
/* Allocate uninitalized data sections: */
.stack : > RAMD1 PAGE = 1
/* Initalized sections go in Flash */
.switch : > FLASH PAGE = 0, ALIGN(8)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */
#if defined(__TI_EABI__)
.init_array : > FLASH, PAGE = 0, ALIGN(8)
.bss : > RAMLS5, PAGE = 1
.bss:output : > RAMLS0_4, PAGE = 0
.bss:cio : > RAMLS5, PAGE = 1
.data : > RAMLS5, PAGE = 1
.sysmem : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.const : > FLASH, PAGE = 0, ALIGN(8)
#else
.pinit : > FLASH, PAGE = 0, ALIGN(8)
.ebss : > RAMLS5 | RAMGS11_15, PAGE = 1
.esysmem : > RAMLS5, PAGE = 1
.cio : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASH PAGE = 0, ALIGN(8)
#endif
SHARERAMGS0 : > RAMGS11_15, PAGE = 1
SHARERAMGS1 : > RAMGS11_15, PAGE = 1
SHARERAMGS2 : > RAMGS11_15, PAGE = 1
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASH,
RUN = RAMLS0_4,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASH,
RUN = RAMLS0_4,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#else
ramfuncs : LOAD = FLASH,
RUN = RAMLS0_4,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#endif
RFFTdata1 : > RAMGS11_15 PAGE = 1, ALIGN = RFFT_ALIGNMENT
RFFTdata2 : > RAMGS11_15 PAGE = 1
RFFTdata3 : > RAMGS11_15 PAGE = 1
RFFTdata4 : > RAMGS11_15 PAGE = 1
RFFTdata5 : > RAMGS11_15 PAGE = 1
/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
}
