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TMS320F28388D: Clock architecture design for F28388D ( USB or EtherCAT - 20Mhz or 25Mhz )

John
Prodigy 230 points
Part Number: TMS320F28388D

Tool/software:

Hello all,

Reading all over the forum and being confused about the clock design on F28388D control card where two clocks of 20MHz and 25MHz are used since the USB boot loader needs the 20MHz as it's hardcoded for that clock( why? ) and for EtherCAT compatibility the 25MHz is needed to be compliant ( I'm already crying ....) 

So, how to simplify this for us? Can I use only a 20MHz clock on our design to be able to use the USB bootloader and at the same time use EtherCAT safely? what are the challenges if we use a 20MHz clock with EtherCAT instead of 25MHz?

Thanks

John

  • 0
    TI__Genius 13025 points

    Hi John,

    USB Bootloader needs 20Mhz crystal since that's configured in boot rom code and cannot be changed now.

    Ethercat PHY clock needs 25Mhz clock which is a requirement driven by design. EtherCAT functional clock inputs CLK25 and CLK100 are sourced by the MCU clocking module either using SYSPLL or AUXPLL. At the SoC level, you have multiple options to choose from regarding what inputs are used for the SYSPLL or AUXPLL as shown below.

    So you can configure AUXPLL with settings needed and route to Ethercat. or you can also have AUXCLKIN routed to AUXPLL and sent to Ethercat while your SYSPLL runs of 20MHz XTAL.

    I would encourage you to have look at 31.2.6.2 Clocking section on 2838x technical reference manual.


    As shown in the diagram you can optionally use the PLL and configure the Div and gate to get the 25Mhz if the accuracy requirements are fulfilled from the 20Mhz crystal you want to use.

  • 0 in reply to Prarthan Bhatt
    Prodigy 230 points

    Hello @Prarthan Bhatt,

    Thank you for the answer, so now as we are designing the board, can we go like below:

    So basically connecting X1 to a 20MHZ clock for running the main CPU clock and the USB and CAN , at the same time using AUXIN/GPIO133 to have the 25MHz for the EtherCAT and EtherNET precisely, going through the clock routings as following:



    The only problem that I see in this design is the 20MHz and 25MHz clocks are now not synchronized as they are derived from two completely different sources, will this cause any problems? -- if yes, what is the solution?

  • 0 in reply to John
    TI__Genius 13025 points

    Hi John,

    Yes the idea should work, I would suggest trying the configuration to test if this is working as intended.

    For clock synchronization, I would suggest that you look at the some kind of synchronization trigger sent to ETHERCAT peripheral from a timed based event to start transaction. I am not familiar with ETHERCAT/NET so I would suggest you make another thread asking about specific challenges you see with clocks not synchronized and how you can use features of the ETHERCAT peripheral to overcome those.

    Thanks!