TMS320F2800157: Missing Clock Detection Test Issue

Hi AHashem,
If the MCLKCLR bit is written (this is a W=1 bit), MCDSTS bit is cleared and OSCCLK source is decided by the OSCCLKSRCSEL bits. Writing to MCLKCLR also clears the MCDPCNT and MCDSCNT counters to allow the circuit re-evaluate missing clock detection. If user wants to lock the PLL after missing clock detection, switch the clock source to INTOSC1 (using OSCCLKSRCSEL register), do a MCLKCLR and re-lock the PLL.

Are you just writing OSCCLKSRCSEL field?  Not running the same function for relocking  as outlined in example code 

You need to follow the proper steps outlined for relocking the PLL
Recommended sequence to set up the system PLL as outlined in TRM :

1. Bypass the PLL by clearing SYSPLLCTL1[PLLCLKEN]. Allow at least 60 NOP instructions for this to take effect.

2. Power down the PLL by writing to SYSPLLCTL1.PLLEN = 0 and allow at least 60 NOP instructions for this to take effect.

3. Select the reference clock source (OSCCLK) by writing to CLKSRCCTL1.OSCCLKSRCSEL. Allow at least 300 NOP instructions for this to take effect.

4. Set the system clock divider to /1 to make sure the fastest PLL configuration by clearing SYSCLKDIVSEL[ PLLSYSCLKDIV].

5. Set the IMULT, REFDIV, and ODIV simultaneously by writing 32-bit value in SYSPLLMULT at once. This automatically enables the PLL. Be sure the settings for the multiplier and dividers do not violate the frequency specifications as defined in the device data sheet.

6. Wait for PLL to lock by polling for lock status bit to go high (SYSPLLSTS.LOCKS = 1).

7. Configure DCC with reference clock as OSCCLK and clock under measurement as PLLRAWCLK, and verify the frequency of the PLL. If the frequency is out of range, do not enable PLLRAWCLK as SYSCLK, stop here and troubleshoot. Refer to Chapter 8 for more information on the configuration and usage.

8. Switch to the PLL as the system clock by setting SYSPLLCTL1[PLLCLKEN] 

Thank you for the detailed response. I followed the recommended procedure for relocking the PLL, and the PLL locks successfully after the test. However, I am encountering an issue where an unhandled NMI is triggered after the test completes.

Specifically, the NMI is mapped to the function ISR_NMI in the vector table:
PieVectTable.NMI_INT = &ISR_NMI;

After performing the test and confirming that the PLL is locked, the software enters the ISR_NMI handler for reasons I cannot determine. Here are the steps I took:

Cleared all NMI flags initially and after the test.
Remapped the NMI vector.
Enabled Missing Clock Detection (MCD).
Simulated a missing clock.
Followed the sequence for relocking the PLL, including clearing the MCLKCLR bit.
Do you have any insights or suggestions on what might be causing this unhandled NMI? Are there additional steps or considerations I should take into account to prevent this issue?

I investigated the issue, and I found out when I enable the test with the following:

 

Hi,

Thank you for the patience.

I am not completely understanding the issue and exact sequence you are following  to get the error - 

AHashem said:

EALLOW;

    ClkCfgRegs.MCDCR.bit.MCLKOFF = 0; /* Turn off missing clock detection */

    ClkCfgRegs.MCDCR.bit.OSCOFF = 1;  /* Turn off oscillator */

    EDIS;

, the NMI comes later on after performing the test

If you turn off MCD, it wont trigger clock fail when you turn off oscillator. I hope you understand that

Now after the above when you want to relock PLL you need to follow below sequence,  : 

1) Configure oscillator source to INTOSC1 - set the clock source first

2)  Re-connect missing clock detection clock source to stop simulating clock failure -  OSCOFF bit back original since you want the clock to be connected back

3) Reset the missing clock detection logic after clock failure - write MCLKCR to clear counters and start fresh

4) Set up PLL control and clock dividers using INTOSC1 as clock source and Lock PLL

You are most likely missing step 2 from above

Thanks,
Prarthan

Hello Prarthan,

Thanks for the answer, here is the steps I follow:

1. Enable Global Interrupt:

   • Enabled global interrupt by setting NmiIntruptRegs.NMICFG.bit.NMIE = 1.

2. Turn Off Missing Clock Detection:

   • Disabled the missing clock detection logic by setting ClkCfgRegs.MCDCR.bit.MCLKOFF = 0.

3. Turn Off Oscillator:

   • Turned off the oscillator to simulate a missing clock by setting ClkCfgRegs.MCDCR.bit.OSCOFF = 1.

4. Setup NMI Handler:

   • Re-mapped the NMI vector to a custom handler by setting PieVectTable.NMI_INT to point to the custom ISR.
   • Cleared all NMI flags by setting NmiIntruptRegs.NMIFLGCLR.all to the current flags and then setting NmiIntruptRegs.NMIFLGCLR.bit.NMIINT = 1.
   • Enabled the NMI global interrupt by setting SysCtl_enableNMIGlobalInterrupt().

5. Simulate Missing Clock:

   • After turning off the oscillator, waited for the NMI to be triggered. Used a flag mg_bNmiFlag to indicate when the NMI handler was executed.

6. Handle NMI in ISR:

   • In the NMI handler, checked for missing clock and clock fail flags by evaluating ClkCfgRegs.MCDCR.bit.MCLKSTS and NmiIntruptRegs.NMIFLG.bit.CLOCKFAIL.
   • If both flags were set, indicated that a clock failure was detected by setting mg_bNmiFlag = true and cleared all NMI flags by setting NmiIntruptRegs.NMIFLGCLR.all to the current flags and NmiIntruptRegs.NMIFLGCLR.bit.NMIINT = 1.

7. Reconfigure Clock and PLL:

   • Reconfigured the clock source to INTOSC1, reset the MCD logic, and re-locked the PLL as follows:
     1. Configured the oscillator source to INTOSC1 by setting ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0x2.
     2. Reconnected the missing clock detection clock source by setting ClkCfgRegs.MCDCR.bit.OSCOFF = 0.
     3. Reset the missing clock detection logic by setting ClkCfgRegs.MCDCR.bit.MCLKCLR = 1.
     4. Bypassed the PLL by setting ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0 and powered down the PLL by setting ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0.
     5. Selected the reference clock source (OSCCLK) by setting ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0.
     6. Set system clock dividers to /1 by setting ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0 and ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV_LSB = 0.
     7. Configured the PLL multipliers and dividers by setting ClkCfgRegs.SYSPLLMULT.all with the appropriate values.
     8. Enabled the PLL by setting ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 1 and waited for it to lock by polling ClkCfgRegs.SYSPLLSTS.bit.LOCKS.
     9. Once the PLL locked, enabled the PLL as the system clock source by setting ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1.

 I think I have convered step 2 you mentioned, following also screenshots from the debugger when it is stuck in ISR NMI 

Hi,

Did you try the software example from c2000ware : sysctl_ex1_missing_clock_detection

What different are you doing then the example? I would compare them one-on-one and try to see what's missing 

I tried the example and it works as intended

I have below questions from the above sequence you mentioned : 

1) Why are you turning MCD off ?

2) Why would you turn off Oscillator in step 3 and then initialize the NMI handler in step 4 ? That doesn't make sense

3) In step 5 what are you exactly doing, you already turned off oscillator and MCD in step 2 and 3 respectively.

Hello,

I know that the example working correctly, I do not think that I make something different than what is done in the example, despite that the code is not working.. 

1) Why are you turning MCD off ?

in step 2 I am not turnning MCD off, I write 0 in ClkCfgRegs.MCDCR.bit.MCLKOFF = 0 to enable MCD as mentioned here:

2) Why would you turn off Oscillator in step 3 and then initialize the NMI handler in step 4 ? That doesn't make sense

I turn off Oscillator in step 3 as done in the example, after Enabling the missing clock detection (MCD) Logic, it Simulate a missing clock

then initialize the NMI handler in step 4, this step could be done anywhere in the code before trigging the interrupt,  as this steps do the following: 

Hello,

AHashem said:

I turn off Oscillator in step 3 as done in the example, after Enabling the missing clock detection (MCD) Logic, it Simulate a missing clock

then initialize the NMI handler in step 4, this step could be done anywhere in the code before trigging the interrupt,  as this steps do the following: 

In the example I can see that the NMI initializations are done before even MCD is enabled and oscillator is turned off



Can you move Step 4 above all the MCD code ?

Thanks

Hello Prarthan,

I moved them but the behaviour still the same, an unhandled NMI fires which make the SW jump to address "0x3fbc34" .

Note: When I flash and run the code in the first time it do not jump to this instruction, but when I make debugger reset and run again it jumps to this address "0x3fbc34" 

Hello,

Please send me you project zipped.

I will try it here and let you know,  hard to debug without actually trying it.

Thanks.