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TMS320F28386S: HRPWM Jump When Coarse Count changes - Not Solved

Part Number: TMS320F28386S

Tool/software:

Hi,

I had marked the thread as closed for the same query earlier. But the problem dosent seem to have gone yet. I have some scope shots here for clarity too. I am trying to demostrate it with a ramp... Note that without the HRPWM, there is clear lack of resolution in the output, with the HRPWM set, the space between two major counts has become a slope indicating HR counts are happening, but they dont seem to meet when the major count changes...

MEP Scale factor for this processor is around 33 and i tried running the SOF function continuously also. As per the referred thread in my previous response, i had made CMPA shadow load which is a requirement for UP-DOWN Counter.

The duty is generated by normalizing the fractional PWM count to 255. Would be great to get some support. Am stuck for a long time with this. 

Thanks

Santhosh

  • Hi Santhosh,

    Can you explain a bit further on major count changes? Does this mean you're going from a CMPA value of 499 to some value 800 for example?

    We have a FAQ on what may be causing common HRPWM issues, please refer to this for setup.

    Best,

    Ryan Ma

  • Thanks for replying,... By Major count, I meant the change in CMPA value. And Minor counts being CMPAHR. My overall CMPA change is only 4-5 counts for the entire waveform shared. we went HRPWM to improve the resolution. I am expecting the HRPWM to bridge between two CMPA values making the Step type of output into a smooth ramp. 

    As per the datasheet, there shall be MEP Scale Factor number of steps provided by the HRPWM within two CMPA Values. so as the factional part goes from 0 to 1, the output should have bridged the region between two CMPA values right ? Which is not what am seeing. my init is something like this...

    HRPWM_setEmulationMode(base, EPWM_EMULATION_FREE_RUN);
        EPWM_setTimeBasePeriod(base, INIT_mPRD_VAL);
        HRPWM_setTimeBaseCounter(base, 0);
    
        EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, INIT_mPRD_VAL >> 1);
        EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B, INIT_mPRD_VAL >> 1);
    
        HRPWM_setTimeBaseCounterMode(base, EPWM_COUNTER_MODE_UP_DOWN);
        HRPWM_disablePhaseShiftLoad(base);
        HRPWM_setClockPrescaler(base, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);
        HRPWM_setPhaseShift(base, (uint32_t)phaseCount << 8U);
        EPWM_enablePhaseShiftLoad(base);
        HRPWM_enablePhaseShiftLoad(base);
        EPWM_enableSyncOutPulseSource(base, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);
        EPWM_setSyncInPulseSource(base, syncInSource);
    
        HRPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_A,
                                              EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD);
        HRPWM_setCounterCompareShadowLoadMode(base, EPWM_COUNTER_COMPARE_B,
                                              EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD);
    
        HRPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A,
                                       EPWM_AQ_OUTPUT_LOW,
                                       EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
        HRPWM_setActionQualifierAction(base, EPWM_AQ_OUTPUT_A,
                                       EPWM_AQ_OUTPUT_HIGH,
                                       EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
    
        HRPWM_disableRisingEdgeDelayCountShadowLoadMode(base);
        HRPWM_disableFallingEdgeDelayCountShadowLoadMode(base);
        EPWM_disableDeadBandControlShadowLoadMode(base);
    
        HRPWM_setRisingEdgeDeadBandDelayInput(base,
                                              EPWM_DB_INPUT_EPWMA);
        HRPWM_setFallingEdgeDeadBandDelayInput(base,
                                               EPWM_DB_INPUT_EPWMA);
    
        HRPWM_setRisingEdgeDelayCountShadowLoadMode(base,
                                                    EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD);
        HRPWM_setFallingEdgeDelayCountShadowLoadMode(base,
                                                    EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD);
    
        EPWM_setDeadBandDelayPolarity(base, EPWM_DB_FED, EPWM_DB_POLARITY_ACTIVE_LOW);
        EPWM_setDeadBandDelayMode(base, EPWM_DB_RED, true);
        EPWM_setRisingEdgeDelayCount(base, INIT_mDEAD_BAND_VAL_RED);
        EPWM_setDeadBandDelayMode(base, EPWM_DB_FED, true);
        EPWM_setFallingEdgeDelayCount(base, INIT_mDEAD_BAND_VAL_FED);
    
        HRPWM_setMEPEdgeSelect(base, HRPWM_CHANNEL_A,
                               HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
        HRPWM_setMEPControlMode(base,HRPWM_CHANNEL_A,HRPWM_MEP_DUTY_PERIOD_CTRL);
    
        HRPWM_setMEPEdgeSelect(base, HRPWM_CHANNEL_B,
                               HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE);
        HRPWM_setMEPControlMode(base,HRPWM_CHANNEL_B,HRPWM_MEP_DUTY_PERIOD_CTRL);
    
        HRPWM_setCounterCompareShadowLoadEvent(base, HRPWM_CHANNEL_A, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);
        HRPWM_setCounterCompareShadowLoadEvent(base, HRPWM_CHANNEL_B, HRPWM_LOAD_ON_CNTR_ZERO_PERIOD);
    
        HRPWM_enableAutoConversion(base);
        HRPWM_enablePeriodControl(base);

    And i update the CMPA/CMPAHR value as 

    HRPWM_setCounterCompareValue(EPWM3_BASE, HRPWM_COUNTER_COMPARE_A, (uint32_t)(fS1Ch3 * 256.0F));

    fS1Ch3 is a floating value of the CMP register. This is as per the hrpwm_ex1_duty_sfo example.

    I had also tried the loading of CMPA and CMPAHR separately too. Same results.

    Thanks

    Santhosh

  • Hi Santhosh, 

    Are you only setting CMPA and CMPAHR?

    Are you following the limitation for reaching the 3 clock cycle boundary at TBPRD / ZRO?

    Best,

    Ryan Ma

  • Hi,

    No my duty starts from 50% and goes up or down. I dont get close to 3 counts issue as mentioned in the datasheet. I did not find any other solution yet. So any other clue should help.

    Thanks,

    Santhosh

  • If you're not using CMPB/CMPBHR, I would recommend still writing at least a value of 1 in the CMPBHR register. 

    Can you confirm that the HR portion you're writing sweeps the full HR i.e. 50.0 -> 50.99% then goes to 60%?

    Is the sync signal coming every period from another PWM? If this is the case, please do not sync every period or zro event because this will cause jitter that you may be seeing. Instead you only need to sync once every so often.

    Best,

    Ryan Ma

  • Hi,

    Loading CMPB and CMPBHR with non zero values

    Yes the HR Portion is going through the full range of values with equal steps. I read back the Compare Value during the CMPA transition.. shown here

    CMPA_FULL is manually calculated by combining the CMPA and CMPA HR. CMPA and CMPA_FULL are on left Y-axis and CMPAHR is on right side Y-axis. I ll check on the sync

    Thanks

    Santhosh

  • For the Sync related point.. yes the two pulses are meant to be in sync in my case, so i use the first PWM as reference (1A) and make Phase as zero for second pwm (2A).... first one is not in sync with any external source. I enable the syncout from EPWM1 and use that as syncin source for EPWM2

    EPWM_enableSyncOutPulseSource(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO); //in epwm1 init

    EPWM_setSyncInPulseSource(EPWM2_BASE, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1); // in epwm2 init..

  • Hi,... 

    I have an update to the thread. The problem seems to have been resolved. The issue was on my hardware as there were 3 channels connected in parallel but they were on different EPWM modules. the last of them was on EPWM9 and EPWM11. realized that these two have no HR capability. the parallel combination of these was the cause of the issue. 

    The left one was from the first two hardware, the one on right was from the last hardware. 

    When i isolated the channel i got good waveforms. Extremely thankful to you for talking me through in this issue. 

    Thanks

    Santhosh