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TMS320F28035: Spike at comp2A pin

Hang Yang
Expert 3031 points
Part Number: TMS320F28035


Tool/software:

Hi experts,

My customer is seeing spike at COMP2A pin like the following:

The frequency of the spike is same to the ADC trigger frequency. Is seems the spike is somehow connected to ADC, therefore we tried to remove some of the SOC. It turns out when we remove SOC1(A2) and SOC8(B4), the spike waveform changes. Removing A2 or B4 SOC would remove the spike at the comp2A pin too:

（Removing B4）

(Removing A2)

If both A2 and B4 SOC are removed, there is no spike

(Removing both A2 and B4)

After removing all SOCs but A2 and B4, there are still spikes but the waveform is different:

Any idea where the spike come from?

Comp2A is connected to COMP1B externally, capacitor on COMP2A pin is 3.3pF, capacitor on ADCs is around 2nF.

Regards,

Hang.

  • 0
    TI__Expert 3031 points

    Hi,

    I've reproduce this on F28035 controlcard. One just need to run Example_2803xAdcSoc, and probe COMP2A. Following are measurements using the example.

    After removing A2 SOC, the spike is weaker:

    Regards,

    Hang.

  • 0 in reply to Hang Yang
    TI__Guru* 81500 points

    Hang,

    This is can be expected based on the input driver(especially if it is high impedance) when the ADC samples the pin voltage.

    Keep in mind that inside the ADC the sampling circuit looks like the below(page 84 from the DS)

    Each time we sample we close the switch, and then the sampling cap Cp begins to charge.  The spike you are seeing is a result of the charge on the Cp.  If the ADC has been un-used for sometime, Cp will be at the native state of 1/2 VREF, ~1.65V.

    So, if your voltage is lower than this you will see a spike up, if higher a spike down.  If the ADC had been converting prior to this the value on Cp would be closer to the previous sample vs what I mention above.

    The settling time of this is then related to how well the input is driven, but in any case we can adjust the ACQPS(sampling time of the ADC) in order to make sure we settle the voltage on the internal S/H cap before converting.

    There is one more factor I want to bring up, and that is how hysteresis is implemented on this device for the comparator.  It is done by a 100kOhm resistor that connects the COMP output to the COMP + input.  If your input impedance is high, then this will also effect the sampling network accordingly.

    We offer a way to disable this hysteresis, which will also remove the feedback resistor from the path.  Below register can be used to do that.  It may be worth trying this as well(assuming you are turning on the COMP2).

    Best

    Matthew

  • 0 in reply to MatthewPate
    TI__Expert 3031 points

    Hi Matthew,

    Thanks for the detailed info on the ADC cap. Is there any suggestion on how to avoid this issue with minimum change the hardware? 

    Regards,

    Hang.

  • 0 in reply to Hang Yang
    TI__Mastermind 24380 points

    Hi Hang,

    Matt is out of office until 07/01. Please expect a delay in his response until then. Thanks for your patience.

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Guru* 81500 points

    Hang,

    I would try the hysteresis disable first, as this will take the 100kohm resistor out of the circuit.  We have a digital filter post comparator customer can use to mimic analog hysteresis if they need it.

    Best,

    Matthew