This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LAUNCHXL-F28379D: CMPSS. Hysteresis needed ?

Part Number: LAUNCHXL-F28379D

Tool/software:

Hello,

I did a first test of CMPSS with OUTPUT XBAR to link OUTH to a GPIO

The input of the CMPSS is a manual potentiometer, the negative input source is the internal DAC.

I am surprised to see the shape of the GPIO I connect OUTH to.

I tested id with the hysteris option X2:

Is the slope I can see on the first graph due to the bounces on OUTH, filtered by the the type of OUTPUT X BAR ?

By the way, what is this type ? Push Pull only?

Is there a mean to access directly to OUTH in the code ?

Also, I did not understand how to choose the hysteresis. What is the "typical hysteresis", mentioned in the reference manual ?

Thank you for your help.

Vincent

  • Hi again Vincent,

    I did a first test of CMPSS with OUTPUT XBAR to link OUTH to a GPIO

    The input of the CMPSS is a manual potentiometer, the negative input source is the internal DAC.

    I am surprised to see the shape of the GPIO I connect OUTH to.

    I am using the cmpss_ex1_asynch example which does this same thing. I am setting hysteresis to zero and I am unable to see your resulting waveform: 

    Is the slope I can see on the first graph due to the bounces on OUTH, filtered by the the type of OUTPUT X BAR ?

    My inputs to CMPSS were a GPIO and the DAC. I suspect that your waveform is caused by the nature of your input which changes relatively slowly. For this reason, it makes sense to use hysteresis to avoid the output bounce. 

    By the way, what is this type ? Push Pull only?

    Yes, this output will be push pull only. 

    Is there a mean to access directly to OUTH in the code ?

    There is a COMPSTS register, could you check to see if that is what you are asking about? 

    Also, I did not understand how to choose the hysteresis. What is the "typical hysteresis", mentioned in the reference manual ?

    The description for this is actually in the datasheet, please see below screenshot: 

    Best Regards,

    Ben Collier

  • Hello Benjamin.

    I m glad to speak you again.

    Thank you for your answers, which help me. But I have more details I want to understand:

    I am using the cmpss_ex1_asynch example which does this same thing. I am setting hysteresis to zero and I am unable to see your resulting waveform

    With a GPIO on input I think I will get the same shape. Do you think that the bounces due to the potentiometer are filtered by the push pull quality of OUTPUT X-BAR ?

    There is a COMPSTS register, could you check to see if that is what you are asking about? 

    Not exactly. I want to access to CTRIPOUTH on the schematic below:

    Have a nice day Benjamin.

    Vincent

  • Vincent,

    Not exactly. I want to access to CTRIPOUTH on the schematic below:

    There is no register that will hold this value exactly. COMPSTS will be closest to achieving this. If the digital filter control registers have the default settings, which are applied after reset, the output of the digital filter (COMPSTS) will lag the ASYNC output of the comparator by only a couple SYSCLK cycles.

    With a GPIO on input I think I will get the same shape. Do you think that the bounces due to the potentiometer are filtered by the push pull quality of OUTPUT X-BAR ?

    Could you test this to make sure? I am also using a launchpad, and my comparator output transitions in less than 1 microsecond. I don't know why you would see anything different unless you have a load on the comparator output.

    Honestly I am not sure what is filtering your comparator output, but it does look like that may be happening.

    Best Regards,

    Ben Collier

  • Could you test this to make sure?

    Of course: see the blue curve (orange one is only to trigger the oscilloscope)

    With potentiometer without hysteresis:

    with GPIO:

    With zoom:

    The transition of the output is about 10ns

    There is no register that will hold this value exactly. COMPSTS will be closest to achieving this. If the digital filter control registers have the default settings, which are applied after reset, the output of the digital filter (COMPSTS) will lag the ASYNC output of the comparator by only a couple SYSCLK cycles

    Thank you for confirming this. I think I can use this for my application.