TMS320F28027F: A SCI_RX interrupt occurs immediately after SCI initialization, then the same interrupt no longer occurs after exiting the handler.

Part Number: TMS320F28027F
Other Parts Discussed in Thread: MOTORWARE, C2000WARE

Tool/software:

Hi.

We use a SCIA module as UART with FIFO by modifying motorware_1_01_00_18.

We encountered some strange behavior. Do you have any idea what is causing this.

I attach below the source code and some screenshots.

1) In line 33, flaming or parity error flags (SCIRXBUF.SCIFFFE, SCIRXBUF.SCIFFPE) are set 1 when enabling TXFIFO.

We don't expect this before enabling RX. At this time, RXFIFO is empty and no RX errors. (SCIFFRX.RXFFST=0, SCIRXST.RXERROR=0)

2) In line 41, An RXFIFO interrupt flag (SCIFFRX.RXFFINT) is set 1 when setting the RXFIFO interrupt level.

Also it confuses us why it is set 1 even though FIFO is empty.

3) In line 89, an SCI reception interrupt occurs after enabling interrupts.

4) RXERROR is set to 1 in the SCI reception interrupt, and MCU no longer receives any data to determine as a reception error and discard continuously.

void main(void)
{
    // Only used if running from FLASH
    // Note that the variable FLASH is defined by the project
    #ifdef FLASH
    // Copy time critical code and Flash setup code to RAM
    // The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart
    // symbols are created by the linker. Refer to the linker files.
    memCopy((uint16_t *)&RamfuncsLoadStart,(uint16_t *)&RamfuncsLoadEnd,(uint16_t *)&RamfuncsRunStart);

    #endif

    pstHalHandle_ = HAL_init(&stHalObj_, sizeof(stHalObj_));

    // disable global interrupts
    CPU_disableGlobalInts(pstHalHandle_->cpuHandle);
    // disable cpu interrupts
    CPU_disableInts(pstHalHandle_->cpuHandle);
    // clear cpu interrupt flags
    CPU_clearIntFlags(pstHalHandle_->cpuHandle);

    HAL_setupClks(pstHalHandle_);
    HAL_setupPll(pstHalHandle_,PLL_ClkFreq_60_MHz);
    HAL_setupPie(pstHalHandle_);
    HAL_setupPeripheralClks(pstHalHandle_);
    HAL_setupGpios(pstHalHandle_);

    // reset SCI
    SCI_reset(pstHalHandle_->sciAHandle);

    // SCIFFTX
    SCI_resetChannels(pstHalHandle_->sciAHandle);
    SCI_enableTxFifoEnh(pstHalHandle_->sciAHandle);
    SCI_clearTxFifoInt(pstHalHandle_->sciAHandle);
    SCI_disableTxFifoInt(pstHalHandle_->sciAHandle);
    SCI_setTxFifoIntLevel(pstHalHandle_->sciAHandle, SCI_FifoLevel_Empty);
    // SCIFFRX
    SCI_resetRxFifo(pstHalHandle_->sciAHandle);
    SCI_clearRxFifoInt(pstHalHandle_->sciAHandle);
    SCI_disableRxFifoInt(pstHalHandle_->sciAHandle);
    SCI_setRxFifoIntLevel(pstHalHandle_->sciAHandle, SCI_FifoLevel_1_Word);

    // SCICCR
    SCI_setNumStopBits(pstHalHandle_->sciAHandle,SCI_NumStopBits_One);
    SCI_setParity(pstHalHandle_->sciAHandle,SCI_Parity_Even);
    SCI_enableParity(pstHalHandle_->sciAHandle);
    SCI_disableLoopBack(pstHalHandle_->sciAHandle);
    SCI_setMode(pstHalHandle_->sciAHandle, SCI_Mode_IdleLine);
    SCI_setCharLength(pstHalHandle_->sciAHandle,SCI_CharLength_8_Bits);

    // SCICTL1
    SCI_disableRxErrorInt(pstHalHandle_->sciAHandle);
    SCI_disable(pstHalHandle_->sciAHandle);
    SCI_disableTxWake(pstHalHandle_->sciAHandle);
    SCI_disableSleep(pstHalHandle_->sciAHandle);
    SCI_enableTx(pstHalHandle_->sciAHandle);
    SCI_enableRx(pstHalHandle_->sciAHandle);

    // SCICTL2
    SCI_disableRxInt(pstHalHandle_->sciAHandle);
    SCI_disableTxInt(pstHalHandle_->sciAHandle);

    // SCIH-SCIL
    SCI_setBaudRate(pstHalHandle_->sciAHandle,SCI_BaudRate_115_2_kBaud);

    // SCIPRI
    SCI_setPriority(pstHalHandle_->sciAHandle,SCI_Priority_FreeRun);

    // enable SCI
    SCI_enable(pstHalHandle_->sciAHandle);

    // regester interrupt handler
    PIE_registerPieIntHandler(pstHalHandle_->pieHandle, PIE_GroupNumber_9, PIE_SubGroupNumber_1, sciARxISR);

    // enable the PIE interrupts associated with the SCI interrupts
    // enable SCIA RX interrupt in PIE
    PIE_enableInt(pstHalHandle_->pieHandle,PIE_GroupNumber_9,PIE_InterruptSource_SCIARX);

    // enable SCI RX interrupts
    // enable SCIA RX FIFO interrupt
    // enable SCIA RX Error interrupt
    SCI_enableRxFifoInt(pstHalHandle_->sciAHandle);
    SCI_enableRxErrorInt(pstHalHandle_->sciAHandle);

    CPU_enableInt(pstHalHandle_->cpuHandle,CPU_IntNumber_9);


    // Enable interrupts
    CPU_enableGlobalInts(pstHalHandle_->cpuHandle);
    // Enable the debugger interrupt
    CPU_enableDebugInt(pstHalHandle_->cpuHandle);

in line 33.

in line 41.

in line 89.

Thanks for your help.