TMS320F28032: ADC sample problem

Hi,

Foriner said:

In these abnormal modules, we grabbed the ADC conversion results to the output voltage at the interrupt level, and found that there was a sampling runout problem, but the ADC sampling results of the normal module did not run, which caused the problem of high output voltage ripple

I'm not sure that I understand what you mean by 'runout', could you please clarify? 

Foriner said:

The figure below has manually converted the ADC conversion result value to the actual voltage value,（output voltage is 400Vdc, use adc result3,result6,result9）

What do you mean by result3, result6, result9? 

Also, could you please share how much the actual ADC output code needs to change to see this output voltage change by 4 volts? 

For example, does the ADC output code increase of 100 codes result in the 4 volt spike that is shown in the graph? 

Is the ADC running with 60MHz ADC Clock? Do you see the same issue with 30MHz ADC clock? Please see the errata for some notes on running with 60 MHz ADC clock, I am not yet sure if your issue is related to this. https://www.ti.com/lit/pdf/sprz295

Also, how long has this design been in production? How many boards have been shipped? Have you always seen this issue with 1% of devices? In a board where the problem is seen, is the problem intermittent or permanent? Is it possible to reproduce the problem easily and consistently?

Best Regards,

Ben Collier

“runout” means Sample jitter，I re-grabbed the ADC sampling data, as shown in the table below, the 2nd and 3rd columns on the left are the original ADC results, and the 4th and 5th columns are the actual voltage values。as you know, The 28032 DSP has a total of 16 ADC conversion results, from 0xB00 to 0xB0F, and we use conversion result 6 and conversion result 9 to store the sample output voltage, which is the address 0xB06 and 0xB09.

The conversion relationship is 1V=3.51cnt

Nearly 10,000 sets of our type of products have been mass-produced, and nearly 50 DSPs have been found to have excess ripple. Since this problem is only available under certain output voltage conditions, we were not aware of it at first, and other series of products in our company have similar problems, but the proportion may not be so high, and the problem is also solved by replacing the DSP, and now we want to turn to TI experts to find a fundamental solution

We are using an ADC sampling frequency of 60M

Sorry for a clerical error here, I correct it, we used 0xB03 and 0x06 to store the sampling results of the output voltage, the above data is 14.2us per interval (ISR frequency = 70K)

Hi,

In the errata that I linked above, it is mentioned that the ADC for this device will have some missing codes (DNL<-1) when using 60 MHz ADC clock, and this issue gets worse at high temperature.

Are you able to try taking the same data with a 30 MHz ADC clock? Do you see the same issue? 

This will help us determine if this errata is the root cause.

Best Regards,

Ben Collier

After changing the sampling frequency of ADC to 30MHz, the problem seems to have been resolved. We are conducting more comprehensive verification to verify if this change has any other impact. We are concerned that reducing the sampling frequency of ADC may lead to a reduction in loop margin. Also, I would like to ask why only a smaller proportion of 2803x DSP ADC clocks have this issue? What is the impact of this clock?

Hi,

Foriner said:

We are concerned that reducing the sampling frequency of ADC may lead to a reduction in loop margin.

I understand, I am interested in hearing an update about if this is acceptable for you. Again, we unfortunately can only guarantee the datasheet performance at 30MHz ADC clock. 

1)ADC Clock = 60MHz, there will be DNL/INL issues at this clock rate.  This is worse at hotter temperatures, but there can still be missing codes and out of spec INL at room temperature. ACQPS(Sample and Hold) window will not have an impact on this parameter.

1a)Only solution to get to the datasheet specifications is to reduce ADC clock rate to 30MHz using the half divider in the ADC regs. 

1b)This is a limitation of the ADC on this device that the internal sub-stages of the ADC cannot settle reliably at full speed. This does not have any relationship to charging the S/H cap to a 12-bit level, so again ACQPS will not have an effect on this issue.

Foriner said:

Also, I would like to ask why only a smaller proportion of 2803x DSP ADC clocks have this issue?

This is likely caused by process variation. Naturally, some units will perform differently than others. 

Foriner said:

What is the impact of this clock?

Please see point 1b above.

Best Regards,

Ben Collier

thank you!

OK， We understand this point, so your suggestion is to set the clock frequency of the ADC to 30MHz for our future 2803x DSP development to ensure the sampling performance of the ADC? Do TI have further plans to optimize the issue of 2803xADC in the next version of 2803x, such as version B? We are currently using TMS320F28004x, TMS320F28003x, and TMS320F280015xDSP on similar products. I would like to confirm if these DSPs have the same issue?

OK，thanks for your professional reply!