TMS320F28375S: POR during surge test

Hi,

Giacomo Gasparini said:

disable (if possibile) the internal MCU undervoltage detection?

This will not be possible.

Giacomo Gasparini said:

It seems that the reset problem is due to a VDDIO=3,3V undervoltage detected inside the MCU but not detectable from MCP120-315 supervisor.

How did you determine this? Are you able to watch your 3.3V power rail with an oscilloscope? 

Giacomo Gasparini said:

Should we need to increase the caps for a specific pin set of the MCU?

This seems like it would be good to try, but it may not work depending on the specific nature of the under voltage event. It would be best to address the root cause of the under voltage event.

Best Regards,

Ben Collier

Hi Giacomo,

Giacomo Gasparini said:

During 1kV differential-mode surge test applied on power supply line the device resets and then restarts (RESC = 0x3, NMIFLG = 0x0).

Adding to Benjamin's observations;

What is the nominal DC voltage prior to surge testing at 1KV? Do you have any snubbers on the IGBT inverter side to handle sudden DC bus transients, MOV suppression, voltage smoothing devices? Can you slowly rise voltage from nominal 400V DC up to 1KV without any issues?

Otherwise Is the 1KV an EMI pulse test or pure DC at 1KV? 

Genatco,

Thank you for pointing out the reset registers, I missed that.

Hi Genatco, Benjamin

the device power section scheme is:

(400Vac 3-phase line power input) -- EMC filter -- diode rectifier -- 560Vdc capacitor bank -- IGBT 3ph inverter bridge -- 3ph brushless motor

so the IGBT inverter is supplied with nominal 560Vdc (not 400Vdc).

The 1 kV 1,2us/50us surge pulse (according IEC 61000-4-5) is injected directly at 400Vac line.

We don't have any snubber or MOV devices on the inverter section.

The problem is the MCU POR reset during this pulse.
The circuit of the XRS pin is the following:
 

We captured the POR during the surge pulse after the removal of 100 ohm resistor in the diagram above: from this test we understood that the supervisor is not triggering any undervoltage on 3.3V rail.
 

- Yellow trace: MCP120 output voltage (nRESET line in the schematic)
- Red trace: nXRS MCU (pin 124)

It doesn't seem related to 3,3V rail undervoltage because otherwise we would have seen it in the yellow trace above. Could it otherwise be a radiated disturbance coupled internally in the MCU? Which is your sopposed fault mode? 

Thank you for your reply.

Regards,

Giacomo

Hi Giacomo, unfortunately Ben is OOO this week.  He should be able to get back to you early next week.  I appreciate your patience and apologize for any inconvenience.

Can you run the same test again but leave 100 Ohm in circuit as that removed pull up resistor (R72) from +3v3 rail. What is value of C59? Seems like 100pF? There is a specification in the TRM for required C value, typically 100nF other C2000 MCU classes.

Hi Genatco,

about the capacitor value: we already tried with C59=100nF and R72=1kohm but the problem remains.

About the new suggested test: we removed R72 and the supervisor MPC120 and we mounted C59=100nF. The result is the following:

  - the yellow trace is the +3.3V_PW_CPU voltage during the surge event; you will see an oscillation around the 3.3V value; the measure has been conducted trying to close the measuring loop as best as possible but we cannot exclude a residual contribution due to irradiated pickup noise; we cannot see an important undervoltage below the POR reset threshold during the event.

 - the red trace is the nXRS pin voltage;

Hi Giacomo,

Giacomo Gasparini said:

The 1 kV 1,2us/50us surge pulse (according IEC 61000-4-5) is injected directly at 400Vac line.

The new test would seem to indicate the MCU is internally resetting itself, often Watchdog timer or BOR caused. Perhaps watch the high voltage DC rail to the inverter during the reset event. If the WD timer is enabled perhaps extend the timeout value, a band aide at best. The WD timer could be triggered if the CPU stops processing C code for whatever reasons, can be due to DC ground rail suddenly bouncing below ground. Countermeasure devices exist that can be placed on the DC rail, e.g. (MOV). Another often effective method is to simply increase the capacitance on DC rail but @560vdc might be daunting if not impossible on existing custom PCB design.

Perhaps the AC surge test is exceeding any would be line transient? Unfamiliar 400VAC 3 phase, in USA 460-480VAC 3 phase is typical.  

Refresher:

3.4.5 Watchdog Reset (WDRS)
The device has a watchdog timer that can optionally trigger a reset if it is not serviced by the CPU within a user specified amount of time. This watchdog reset (WDRS) produces an XRS that lasts for 512 INTOSC1 cycles. After a watchdog reset, the WDRSn bit in RESC is set.

3.4.2 External Reset (XRS)
The external reset (XRS) is the main chip-level reset for the device. It resets the CPU, all peripherals and I/O pin configurations and most of the system control registers. There is a dedicated open-drain pin for XRS. This pin may be used to drive reset pins for other ICs in the application and may itself be driven by an external source. The XRS is driven internally during watchdog, NMI, and power-on resets. The XRSn bit in the RESC register will be set whenever XRS is driven low for any reason. This bit is then cleared by the boot ROM.

RESC: 3.14.4.26 RESC Register (Offset = 80h)

Bit 0: POR R1h If this bit is set, indicates that the device was reset by POR/BOR.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: POR
www.ti.com System Control and Interrupts

Bit 1: XRSn R1h If this bit is set, indicates that the device was reset by XRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Reset type: POR

Bit 2: WDRSn R0h If this bit is set, indicates that the device was reset by WDRSn.
Writing a 1 to this bit will force the bit to 0
Writing of 0 will have no effect.
Note: [1] A bit inside WD module also provides the same information. This
bit is present to keep things consistent. This register is a one-stop
shop for the software to know the reset cause for the C28x core.
Reset type: POR

Dear Genatco,

thank you for detailed reply.

• Does TMS320F28375 have BOR logic? The doc seems to refer only to POR logic.
• In first message I reported the content of those register after POR event: RESC = 0x3, NMIFLG = 0x0. So the WDRSn field is not set so we would exclude a Watchdog intervention.

Any other ideas to investigate or attenuate the issue?

Thank you again

Hi Giacomo,

It would seem a POR reset event due to internal logic detecting a perceived BOR. Perhaps check WD register bits too, even disable him though beware hardware could be stomped on if indeed the Dog came to the rescue left no trace evidence application going bonkers. For instance, BOR and WD both occurred caused a POR reset, would RESC register bits be set or cleared? Suppose it would depend on the severity of the DC power perturbation event/s the MCU reset logic detects. Are you certain only one 50µs pulse @1KV occurs inside any test period? More than double the typical line voltage (400VAC) an 500VAC MOV might likely explode depending on device dissipation ability and PCB mounting. The DC supply AC rectifier diodes must be huge to withstand such EMF pulse, perhaps check PRV 1.5-2KV range to be safe.

Giacomo Gasparini said:

Does TMS320F28375 have BOR logic?

It would seem logical C2000 MCU class have BOR detection, check the x75 TRM to be sure.

Dear guys,

the TRM doens't mention BOR threshold but only POR threshold. Does the POR threshold work both in the startup and powerdown phases?

By the way in our application we disabled the WD so the only likely reset source is POR(BOR) at 2.3V threshold.

Are there any other advices?

Giacomo,

There isn't a documented BOR level since it will vary from device to device, but it is possible to have a BOR when you are outside of recommended operating conditions. In my experience, BOR can be encountered around 2.8V, but that will vary. If you want to do a quick test, you could connect VDDIO to some voltage source and slowly lower it until you have a reset. You should encounter a reset above 2.3V. 

Best Regards,

Ben Collier

Thank you Ben,

I understood that the BOR circuit is included in the MCU and the test you advice could confirm this fact furtherly.

A part from this fact, in order to solve the problem how can we proceed?

Thank you again,

Giacomo.

Hi Giacomo.

Can you post a schematic of the PCB +3v3 power circuit and how high voltage or any other MCU supply rail DC is being stepped down for MCU use?  Ideally, we try to design circuits arresting DC transients, not allow them to vector into the sensitive silicon devices. Hence suggested MOV even if to determine the point/s of causation on GPIO and VDD rails.

Perhaps Littlefuse makes a high voltage MOV with radial leads tack into the circuit, otherwise you might try a series varistor on HV rail. We have tested varistors slowing inrush current up to 250VDC 30A, also help smooth DC ripple current. Have maximum capacitance power dissipation value and series resistance drops under current demand such as initial power up cycle. 

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