Other Parts Discussed in Thread: C2000WARE, SYSCONFIG
Tool/software:
TMS320F28375D controller is used to generate 0.9 to 1.1 MHz high resolution pwm (HRPWM) signal with 1Khz step resolution using system clock of 200mHZ and EPWM clock of 100MHz.
The problem is that there is jitter in duty cycle either in rising or in falling edge of signal with approx 10-12ns seen in oscilloscope having bandwidth of 500MHz.
For this following configuration is used for epwm6A.
EPwm6Regs.TBPRD = 99;
EPwm6Regs.TBPRDHR = 0;
EPwm6Regs.TBPHS.bit.TBPHS = 0x0000;
EPwm6Regs.TBCTL.bit.FREE_SOFT = 3;
EPwm6Regs.TBCTL.bit.PHSDIR = 0;
EPwm6Regs.TBCTL.bit.CLKDIV = 0;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm6Regs.TBCTL.bit.SWFSYNC = 1;
EPwm6Regs.TBCTL.bit.SYNCOSEL = 0;
EPwm6Regs.TBCTL.bit.PRDLD = 0;
EPwm6Regs.TBCTL.bit.PHSEN = 0;
EPwm6Regs.TBCTL.bit.CTRMODE = 00;
EPwm6Regs.TBSTS.bit.CTRMAX = 0;
EPwm6Regs.TBSTS.bit.SYNCI = 0;
EPwm6Regs.TBSTS.bit.CTRDIR = 0;
EPwm6Regs.CMPCTL.bit.SHDWBFULL = 0;
EPwm6Regs.CMPCTL.bit.SHDWAFULL = 0;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm6Regs.CMPCTL.bit.LOADBMODE = 0x00;
EPwm6Regs.CMPCTL.bit.LOADAMODE = 0x00;
EPwm6Regs.CMPA.bit.CMPA = 50;
EPwm6Regs.CMPB.bit.CMPB = 50;
EPwm6Regs.AQCTLA.bit.CBD = 00;
EPwm6Regs.AQCTLA.bit.CBU = 00;
EPwm6Regs.AQCTLA.bit.CAD = 00;
EPwm6Regs.AQCTLA.bit.CAU = 01;
EPwm6Regs.AQCTLA.bit.PRD = 00;
EPwm6Regs.AQCTLA.bit.ZRO = 10;
EPwm6Regs.AQCTLB.bit.CBD = 00;
EPwm6Regs.AQCTLB.bit.CBU = 01;
EPwm6Regs.AQCTLB.bit.CAD = 00;
EPwm6Regs.AQCTLB.bit.CAU = 00;
EPwm6Regs.AQCTLB.bit.PRD = 00;
EPwm6Regs.AQCTLB.bit.ZRO = 10;
EPwm6Regs.ETSEL.bit.SOCBEN = 0;
EPwm6Regs.ETSEL.bit.SOCBSEL = 0;
EPwm6Regs.ETSEL.bit.SOCAEN = 0;
EPwm6Regs.ETSEL.bit.SOCASEL = 0;
EPwm6Regs.ETSEL.bit.INTEN = 0;
EPwm6Regs.ETSEL.bit.INTSEL = 0;
EPwm6Regs.AQCSFRC.bit.CSFB = 01;
EPwm6Regs.AQCSFRC.bit.CSFA = 01;
EPwm6Regs.HRCNFG.all = 0x0;
EPwm6Regs.HRCNFG.bit.EDGMODE = HR_FEP;
EPwm6Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm6Regs.HRCNFG.bit.HRLOAD = HR_CTR_PRD;
EPwm6Regs.HRCNFG.bit.EDGMODEB = HR_FEP;
EPwm6Regs.HRCNFG.bit.CTLMODEB = HR_CMP;
EPwm6Regs.HRCNFG.bit.HRLOADB = HR_CTR_PRD;
EPwm6Regs.HRCNFG.bit.AUTOCONV = 0;
EPwm6Regs.HRPCTL.bit.TBPHSHRLOADE = 0;
EPwm6Regs.HRMSTEP.bit.HRMSTEP = 28;
EPwm6Regs.HRPCTL.bit.HRPE = 1;
Note:
//--------Settings for different frequency--------//
//-----------for 1MHz------------//
EPwm6Regs.TBPRD = 99;
EPwm6Regs.TBPRDHR = 0;
EPwm6Regs.CMPA.bit.CMPA = 50;
EPwm6Regs.CMPA.bit.CMPAHR = 0;
//-----------for 1.1MHz------------//
EPwm6Regs.TBPRD = 89;
EPwm6Regs.TBPRDHR = 59577;
EPwm6Regs.CMPA.bit.CMPA = 45;
EPwm6Regs.CMPA.bit.CMPAHR = 3386;
//-----------for 0.9MHz------------//
EPwm6Regs.TBPRD = 110;
EPwm6Regs.TBPRDHR = 7281;
EPwm6Regs.CMPA.bit.CMPA = 55;
EPwm6Regs.CMPA.bit.CMPAHR = 4110;
//---------------------------------//
So, what could be the reason for jitter?
We observed that no jitter with 200 Mhz EPWM clock and is it safe to use 200Mhz clock for EPWM.