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TMS320F28375D: TMS320F28375D EPWM HRPWM

Part Number: TMS320F28375D
Other Parts Discussed in Thread: C2000WARE, SYSCONFIG

Tool/software:


TMS320F28375D controller is used to generate 0.9 to 1.1 MHz high resolution pwm (HRPWM) signal with 1Khz step resolution using system clock of 200mHZ and EPWM clock of 100MHz.

The problem is that there is jitter in duty cycle either in rising or in falling edge of signal with approx 10-12ns seen in oscilloscope having bandwidth of 500MHz.
For this following configuration is used for epwm6A.  

EPwm6Regs.TBPRD = 99;
EPwm6Regs.TBPRDHR = 0;
EPwm6Regs.TBPHS.bit.TBPHS = 0x0000;
EPwm6Regs.TBCTL.bit.FREE_SOFT = 3;
EPwm6Regs.TBCTL.bit.PHSDIR = 0;
EPwm6Regs.TBCTL.bit.CLKDIV = 0;
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 0;
EPwm6Regs.TBCTL.bit.SWFSYNC = 1;
EPwm6Regs.TBCTL.bit.SYNCOSEL = 0;
EPwm6Regs.TBCTL.bit.PRDLD = 0;
EPwm6Regs.TBCTL.bit.PHSEN = 0;
EPwm6Regs.TBCTL.bit.CTRMODE = 00;

EPwm6Regs.TBSTS.bit.CTRMAX = 0;
EPwm6Regs.TBSTS.bit.SYNCI  = 0;
EPwm6Regs.TBSTS.bit.CTRDIR = 0;

EPwm6Regs.CMPCTL.bit.SHDWBFULL = 0;
EPwm6Regs.CMPCTL.bit.SHDWAFULL = 0;
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm6Regs.CMPCTL.bit.LOADBMODE = 0x00;
EPwm6Regs.CMPCTL.bit.LOADAMODE = 0x00;

EPwm6Regs.CMPA.bit.CMPA = 50;
EPwm6Regs.CMPB.bit.CMPB = 50;

EPwm6Regs.AQCTLA.bit.CBD = 00;
EPwm6Regs.AQCTLA.bit.CBU = 00;
EPwm6Regs.AQCTLA.bit.CAD = 00;
EPwm6Regs.AQCTLA.bit.CAU = 01;
EPwm6Regs.AQCTLA.bit.PRD = 00;
EPwm6Regs.AQCTLA.bit.ZRO = 10;

EPwm6Regs.AQCTLB.bit.CBD = 00;
EPwm6Regs.AQCTLB.bit.CBU = 01;
EPwm6Regs.AQCTLB.bit.CAD = 00;
EPwm6Regs.AQCTLB.bit.CAU = 00;
EPwm6Regs.AQCTLB.bit.PRD = 00;
EPwm6Regs.AQCTLB.bit.ZRO = 10;

EPwm6Regs.ETSEL.bit.SOCBEN = 0;
EPwm6Regs.ETSEL.bit.SOCBSEL = 0;
EPwm6Regs.ETSEL.bit.SOCAEN = 0;
EPwm6Regs.ETSEL.bit.SOCASEL = 0;

EPwm6Regs.ETSEL.bit.INTEN = 0;
EPwm6Regs.ETSEL.bit.INTSEL = 0;

EPwm6Regs.AQCSFRC.bit.CSFB = 01;
EPwm6Regs.AQCSFRC.bit.CSFA = 01;

EPwm6Regs.HRCNFG.all = 0x0;
        
EPwm6Regs.HRCNFG.bit.EDGMODE = HR_FEP;           
EPwm6Regs.HRCNFG.bit.CTLMODE = HR_CMP;           
EPwm6Regs.HRCNFG.bit.HRLOAD = HR_CTR_PRD;
       
EPwm6Regs.HRCNFG.bit.EDGMODEB = HR_FEP;          
EPwm6Regs.HRCNFG.bit.CTLMODEB = HR_CMP;          
EPwm6Regs.HRCNFG.bit.HRLOADB = HR_CTR_PRD;
        
EPwm6Regs.HRCNFG.bit.AUTOCONV = 0;
EPwm6Regs.HRPCTL.bit.TBPHSHRLOADE = 0;           
EPwm6Regs.HRMSTEP.bit.HRMSTEP = 28;

EPwm6Regs.HRPCTL.bit.HRPE = 1;

Note:
//--------Settings for different frequency--------//
//-----------for 1MHz------------//
EPwm6Regs.TBPRD = 99;
EPwm6Regs.TBPRDHR = 0;
EPwm6Regs.CMPA.bit.CMPA = 50;
EPwm6Regs.CMPA.bit.CMPAHR = 0;
//-----------for 1.1MHz------------//
EPwm6Regs.TBPRD = 89;
EPwm6Regs.TBPRDHR = 59577;
EPwm6Regs.CMPA.bit.CMPA = 45;
EPwm6Regs.CMPA.bit.CMPAHR = 3386;
//-----------for 0.9MHz------------//
EPwm6Regs.TBPRD = 110;
EPwm6Regs.TBPRDHR = 7281;
EPwm6Regs.CMPA.bit.CMPA = 55;
EPwm6Regs.CMPA.bit.CMPAHR = 4110;
//---------------------------------//

So, what could be the reason for jitter?
We observed that no jitter with 200 Mhz EPWM clock and is it safe to use 200Mhz clock for EPWM.
                  

  • Hello,

    Have you already compared your configurations to our C2000Ware examples? (C:\ti\c2000\C2000Ware_5_02_00_00\driverlib\f2837xd\examples\cpu1\hrpwm) and double checked with our Technical Reference Manual HRPWM chapter? 

    I would also note that developing with our SysConfig GUI also can help to catch some warnings/errors on incompatible HRPWM settings.

    Could you elaborate on what target EPWM output you are wanting? A quick diagram is always helpful to visualize the timings and desired output.

    For the HR settings are you wanting to only control the falling edge with HR (high res duty control) and then control the time base period with HR (high res frequency control)? Can you try enabling autoconversion and making sure to use up-down count with the actions centered around PRD, and use shadow loading on CTR = 0 AND CTR = PRD?

    Best Regards,

    Allison

  • Thanks Allison for the prompt reply,

    I have tried with up-down count mode using auto conversion enabled and it resolved my issue.