Tool/software:
Dear champs,
1. In our controlcard, there are 3 PHYs (1 EtherNET, 2 EtherCAT), about 3 sets of clock selection circuits:
For example:
1) P0_PHY_CLK select P0_25MHZ_CLK, P1_PHY_CLK select P1_25MHZ_CLK, and F2328x_CLK select 20MHZ _CLK.
----EtherNET-PHY is always ENET_PHY_CLK, so that the DSP and the three PHYs are not on the same frequency;
2) P0_PHY_CLK select P0_25MHZ_CLK, P1_PHY_CLK select P1_25MHZ_CLK, and F2328x_CLK select F2328x_25MHZ _CLK.
----In this way, the DSP and the 3 PHYs are all at the same frequency;
3) P0_PHY_CLK SELECT MCU_GPIO154, P1_PHY_CLK SELECT P1_25MHZ_CLK, F2328x_CLK SELECT 20MHZ _CLK
----MCU_GPIO154 is a clock signal generated internally by the DSP, so that the DSP is at the same frequency as EtherCAT-PHY0 and not at the same frequency as EtherCAT-PHY1 and EtherNET-PHY.
4) P0_PHY_CLK select MCU_GPIO154, P1_PHY_CLK select MCU_GPIO154, and F2328x_CLK select 20MHZ _CLK.
----In this way, the DSP is not at the same frequency as the EtherNET-PHY, and is at the same frequency as the two EtherCAT-PHY.
Now customer need to check:
1) Can the 3 sets of clock selection circuits be combined at will? Any requirements or suggestions?
2) Do EtherNET-PHY and EtherCAT-PHY have the same requirements for clock signals? Does EtherNET also recommend that it is best to co-frequency with a DSP?
Could you give some advice on this? Thank you!
Julia
