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Original question:

TMS320F2800157: RAM ECC Test

TMS320F2800132: ECC RAM test

Manu36
Expert 1360 points
Part Number: TMS320F2800132
Other Parts Discussed in Thread: C2000WARE

Tool/software:

Dear support team.

I try to add ECC RAM test in my project.

I start from the example below:

C2000Ware_MotorControl_SDK_5_02_00_00\c2000ware\libraries\diagnostic\f280013x\examples\sdl_ex_flash_ecc_test

But I face some issue / have questions.

In function runCorrectableECCTest:

      //
        // Put the M0RAM into test mode so we can write to the data without
        // updating the ECC, flip a bit, and put the RAM back into the normal
        // functional mode.
        //
        testRAMLogic(MEMCFG_SECT_M0, MEMCFG_TEST_WRITE_DATA,
                     (uint32_t)&m0Data, (RAM_DATA_SINGLE_BIT << index));

This function work as espected and trig the error ISR (correctable error) but:

   //
        // Put the M0RAM into test mode so we can write to the ECC bits
        // directly, flip multiple bits, and put the RAM back into the
        // normal functional mode.
        //
        testRAMLogic(MEMCFG_SECT_M0, MEMCFG_TEST_WRITE_ECC,
                     (uint32_t)&m0Data, (RAM_ECC_SINGLE_BIT << index));

This one didn't trig error ISR but NMIisr so I'm a little bit confused.

The comment says "flip multiple bits" so if right, it is not correctable and it is normal to trig NMI, but for me the code only flip single bit.

Please let me know where is the error? In the example?

Regards.

  • 0
    Expert 1360 points

    Hello,

    I made intensive test and I also modify the example code to handle also LS0 and M1.

    First issue issue I faced is:

    testing single bit ECC using testRAMLogic(MEMCFG_SECT_M0, MEMCFG_TEST_WRITE_ECC, (uint32_t)&m0Data, (RAM_ECC_SINGLE_BIT << index)) trigs NMIisr instead of errorISR.

    This is true for both ECC for lower or upper 16 bits of data.

    Can you explain why?

    Second issue is:

    M0 and M1 react differently on the test:

            testRAMLogic(ramSection, MEMCFG_TEST_WRITE_ECC,
                     (uint32_t)ptradress, (RAM_ECC_SINGLE_BIT << index));

    and :

            testRAMLogic(ramSection, MEMCFG_TEST_WRITE_ECC,
                     (uint32_t)ptradress, (RAM_ECC_MULTI_BIT << index));

    For M1 there is a difference beetween the expected adress and the return adress (need to add 1 to the expected adress as it was on the original example) but this is not true for M0.

    Can you explain why there is a difference? Can it be related to the adress which is choosen by the linker (alignment issue)?

    Regards.

  • 0 in reply to Manu36
    TI__Guru** 115881 points

    Manu,

    Do you have a sample project which I can use to reproduce this issue ?

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 1360 points

    Hello,

    I think the easiest is to start from the following example:

    C2000Ware_MotorControl_SDK_5_02_00_00\c2000ware\libraries\diagnostic\f280013x\examples\sdl_ex_flash_ecc_test

    Regards.

  • 0 in reply to Manu36
    Expert 1360 points

    sory this is not the correct example, the correct one is:

    C2000Ware_MotorControl_SDK_5_02_00_00\c2000ware\libraries\diagnostic\f280013x\examples\sdl_ex_ram_ecc_parity_test

    Regards.

  • 0 in reply to Manu36
    Expert 1360 points

    A few more input,

    Test using M1 trigs the error ISR as expected and nedd to add 1 to the adress => fully OK according to the example.

    Test using M0 trigs multiple NMI instead of error ISR but sounds like it is a different error that probably explain tat there is no need to add 1 to adress. So in fact both issue are related and I suspect this is related to the data position....

  • 0 in reply to Manu36
    Expert 1360 points

    I think I found the origin of the issue, the issue is when the test is performed in the same location than the .stack....

    I will try to rewrite some code as suggested in the last post of this discussion:

    https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1360578/tms320f2800157-ram-ecc-test

    Exept if you have other suggestions.

    Regards.

  • +1 in reply to Manu36
    Expert 1360 points

    I have been able to solve my issue by writing a specific testRAMLogic function for the M0 RAM where the stack was located.

    I remove the call to other function and just copy the code and also made some simplification because I will use this one only for M0.

    All is OK now!

    Regards.