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TMS320F28374S: Abnormal drive waveform occurred under PWM phase shift control

Yue Gu
Prodigy 20 points
Part Number: TMS320F28374S

Tool/software:

We config the EPWM1 module of DSP1 to output SYNC signal when CTR=0, which is further used to synchronize the EPWM1 module of another chip (DSP2).

The two DSP chips both use up and down counting mode, the TBPRD register are both 2500. The output of PWM  is set to be low when CTR=CMP in the up-count mode, while the output is high  when CTR=CMP in the down-count mode.

The TBPHS reload of DSP2 chip is enabled and the phase shift value is set to 10U, instead of zero.

It is found that when the duty cycle of DSP2 is very small, it outputs an abnormal normal high level suddenly. As follows.

As can be seen from the figure above, after the synchronization signal in the middle position arrives, the EPWM count register of DSP2 should be loaded as 10, and the corresponding TBCTR should be close to zero.

Theoretically, the output PWM duty cycle at this time should be approximately 0, but the result is the high level PWM with a duty cycle of approximately 1

There are a lot of similar problems with driver loss caused by phase shift on the forum, but they all occur when the phase shift is changed dynamically.

But in my application the value of TBPHS of EPWM1 module is fixed with the value of 10U in DSP2.

Why does this happen? 

I analyze whether it is because as shown in the figure above, assuming that the TBCMPA register at this time may be 6, the data of the TBCTR register will be directly updated from 4 to 10 after the synchronization signal comes, and the comparison match of the rising edge will be missed.

As a result, the high level has not been pulled down until the comparison of the falling edge matches the PWM pull point, resulting in a PWM high level output of nearly one cycle

I wonder if that's the reason?

The test has seen the synchronization signal, which is very stable in every period, then each period will trigger the EPWM1 module of DSP2 to perform phase shift operation.

So the next time the phase shift signal comes, the count register should be very close to the set TBPHS register value? That way, it shouldn't miss this match.

After a PWM cycle, how much difference can the TBCTR make with the theoretical value? In theory, if the crystal clock is very stable, after a synchronous phase shift operation, the data of the count register and the data of the phase shift register are the same every time the phase shift signal comes.

  • 0
    TI__Expert 5430 points

    Hi, 

    Please note most of the team were OoO due to the US holiday. Kindly expect a response in the next 2 days.

  • 0
    TI__Mastermind 21570 points

    Hello,

    Thank you for the patience. Could you please share both EPWM configurations? What are the action qualifiers for them? Did you check the EPWM registers to be sure the configurations match what you are expecting based on your initializations? 

    Specifically, what are the settings for the EPWM on the DSP2? How are you connecting the sync pulse from DSP1 to DSP2 and using it to shift the waveform?

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Prodigy 20 points

    Thank you for your reply.

    The configuration of EPWM1 of Chip1is as follow.

    EPWM_setClockPrescaler(EPWM1_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

EPWM_setTimeBasePeriod(EPWM1_BASE, INV_PWM_PERIOD);
EPWM_setTimeBaseCounter(EPWM1_BASE, 0U);
EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN);

EPWM_disablePhaseShiftLoad(EPWM1_BASE);
EPWM_setPhaseShift(EPWM1_BASE, 0U);
EPWM_setSyncOutPulseMode(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO);

EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_PERIOD);
EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, 0);

// Set actions
EPWM_setActionQualifierAction(EPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(EPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

EPWM_setDeadBandDelayMode(EPWM1_BASE, EPWM_DB_RED, false);
EPWM_setDeadBandDelayMode(EPWM1_BASE, EPWM_DB_FED, false);

EPWM_disablePhaseShiftLoad(EPWM1_BASE);
EPWM_setPhaseShift(EPWM1_BASE, 0U);
EPWM_setSyncOutPulseMode(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO);


SysCtl_setSyncOutputConfig(SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT);
XBAR_setOutputMuxConfig(XBAR_OUTPUT1, XBAR_OUT_MUX14_EXTSYNCOUT);
XBAR_enableOutputMux(XBAR_OUTPUT1, XBAR_MUX14);
XBAR_invertOutputSignal(XBAR_OUTPUT1, TRUE);
GPIO_setPinConfig(GPIO_58_OUTPUTXBAR1);

    And the configuration of EPWM1 of Chip2 is as follow.

    EPWM_setClockPrescaler(EPWM1_BASE, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

EPWM_setTimeBasePeriod(EPWM1_BASE, INV_PWM_PERIOD);
EPWM_setTimeBaseCounter(EPWM1_BASE, 0U);
EPWM_setTimeBaseCounterMode(EPWM1_BASE, EPWM_COUNTER_MODE_UP_DOWN);

EPWM_disablePhaseShiftLoad(EPWM1_BASE);
EPWM_setPhaseShift(EPWM1_BASE, 0U);
EPWM_setSyncOutPulseMode(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO);

EPWM_setCounterCompareShadowLoadMode(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_PERIOD);
EPWM_setCounterCompareValue(EPWM1_BASE, EPWM_COUNTER_COMPARE_A, 0);

// Set actions
EPWM_setActionQualifierAction(EPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW, EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
EPWM_setActionQualifierAction(EPWM1_BASE, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH, EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

EPWM_setDeadBandDelayMode(EPWM1_BASE, EPWM_DB_RED, false);
EPWM_setDeadBandDelayMode(EPWM1_BASE, EPWM_DB_FED, false);

EPWM_disablePhaseShiftLoad(EPWM1_BASE);
EPWM_setPhaseShift(EPWM1_BASE, 0U);
EPWM_setSyncOutPulseMode(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO);


XBAR_setInputPin(XBAR_INPUT5, 66);
EPWM_disablePhaseShiftLoad(EPWM1_BASE);
EPWM_setPhaseShift(EPWM1_BASE, 10U);
EPWM_setCountModeAfterSync(EPWM1_BASE, EPWM_COUNT_MODE_UP_AFTER_SYNC);
EPWM_setSyncOutPulseMode(EPWM1_BASE, EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO);

EPWM_enablePhaseShiftLoad(EPWM1_BASE);

    The sync pluse is sent out from GPIO58 through the X-BAR. It has been seen from the oscilloscopes and shown above.

    When I change the value of  EPWM_O_TBPHS from 10U to 0U, the output becomes normal. I don't know why.

  • 0 in reply to Yue Gu
    TI__Mastermind 21570 points

    Hi Yue,

    Thanks for attaching the configurations. Reviewing the information, I wanted to point out that if the issue is that there is an action (set PWM high or clear PWM low) missed as a result of a sync pulse, then you will need to implement software to carry out the action that is missed. This can happen when using variable phase shift in particular. Please review this past thread and let me know if this applies to you:

    https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1312604/tms320f28379d-tms320f28379d-phase-shift-pwm-missing-pulse 

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Prodigy 20 points

    Much thanks for your reply.

    I use constat phase shift instead of variable phase shift in TBPHS. That's why I was confused. If there are other possible reason?

  • 0 in reply to Yue Gu
    TI__Mastermind 21570 points

    Hi Yue,

    Is the missed action happening with every sync pulse?

    Even without a variable phase shift, if the AQ and TBPHS and CMP values align in a certain way (as I explained in the other thread), this can cause the counter to jump over the action qualifier event and miss it.

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Prodigy 20 points

    Hi Allson,

    The control system would trigger fault protection when this misses action happens. And each time the system start, the fault protection would then be triggered, which means this missed action also happened.

    When I changed the TBPHS from 10U to 0U, the PWM became normal.

  • 0 in reply to Yue Gu
    TI__Mastermind 21570 points

    Hi Yue,

    Is the missed action always when the TBCTR < CMPA < TBPHS (or opposite)? Have you tried implementing T1 and T2 as I suggested in the related thread?

    Best Regards,

    Allison