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TMS320F2800157: TMS320F2800157: SRAM/FLASH ECC Correctable error threshold

Part Number: TMS320F2800157

Tool/software:

I have the following questions:

1. Regarding the configuration for the Flash ECC correctable error threshold and the RAM correctable error threshold, are they both configured using the same register, the CERRTHRES Register?

2. In SRAM ECC, how can I ensure that it is enabled during the runtime of the project? I know it is enabled by default after reset, but I need to check the register to make sure it is enabled and enable it if it is not. As I see ECC_ENABLE register for FLASH only.

3. Similarly, for SRAM Parity, how can I ensure that it is enabled during the runtime of the project?

4. Regarding the PieVectTable, I am confused about whether it is protected by Parity or not. The datasheet states that it is not protected, however, in the examples, it is protected by parity and there is a test for this. Could you clarify this?

  • Hello,

    Any updates?

  • Hi,

    1. Regarding the configuration for the Flash ECC correctable error threshold and the RAM correctable error threshold, are they both configured using the same register, the CERRTHRES Register?

    Yes, it's same for SRAM and Flash.

    2. In SRAM ECC, how can I ensure that it is enabled during the runtime of the project? I know it is enabled by default after reset, but I need to check the register to make sure it is enabled and enable it if it is not. As I see ECC_ENABLE register for FLASH only.

    ECC_ENABLE feature is only available for Flash. For RAM, it's always enable. 

    3. Similarly, for SRAM Parity, how can I ensure that it is enabled during the runtime of the project?

    Just like ECC, Parity is always enable.

    4. Regarding the PieVectTable, I am confused about whether it is protected by Parity or not. The datasheet states that it is not protected, however, in the examples, it is protected by parity and there is a test for this. Could you clarify this?

    It has parity. Please see below snapshot from device TRM.

    Regards,

    Vivek Singh