TMS320F28P650DH: DMA settings

Tool/software:

Hi Guys,

Thanks in advance for your efforts to help me with the following issue 

I want to use the DMA in the device tms320f28p650dh for the following transfers.

I have a source array of uint32 s_arr[8] and destination array of unint32 d_arr[16]. The transfer should be like two copies of srource array into destination array without any intteruption to CPU and continous mode.

-----(Later on I will use the source array as the ADCPPBSUM and COUNT values, so that I have two consecutive results stored for further processings but for now any array in RAM is fine)---- not needed now. 

I am using the control card to monitor whether the transfer is sucessful. I tried many settings, but seems no transfer of memory happens though the ACTIVE ADDR pointers are correct in the debug session. Here is my DMA configuration-

extern Uint32 adcBuffer_dst[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
extern Uint32 adcBuffer_src[8] = {50,51,52,53,54,55,56,57};

After a transfer I wish the result as ----- adcBuffer_dst[16] = {50,51,52,53,54,55,56,57,   50,51,52,53,54,55,56,57};

void initDMA(void)
{
uint16_t i;
__eallow();

DmaRegs.DMACTRL.bit.HARDRESET = 1;
asm(" NOP");
asm(" NOP");
DmaRegs.DMACTRL.bit.HARDRESET = 0;

//Within a Burst
DmaRegs.CH1.BURST_SIZE.all = 7; // 8 bursts per transfer
DmaRegs.CH1.SRC_BURST_STEP = 1; // Source address increment by 1 
DmaRegs.CH1.DST_BURST_STEP = 1; // Destination address incremented by 1

DmaRegs.CH1.TRANSFER_SIZE = 1; // 2 bursts in one transfer
DmaRegs.CH1.SRC_TRANSFER_STEP = -7; // source address back to s[0]
DmaRegs.CH1.DST_TRANSFER_STEP = 0; // Destination address continue

DmaRegs.CH1.CONTROL.bit.ERRCLR = 1;

//DmaRegs.CH1.DST_WRAP_SIZE = -1; // Wrap destination address after BUFFER_SIZE
//DmaRegs.CH1.DST_WRAP_STEP = 0; // Step back to start of buffer
DmaRegs.CH1.SRC_WRAP_SIZE = -1; // Wrap destination address after BUFFER_SIZE
DmaRegs.CH1.SRC_WRAP_STEP = 0; // Step back to start of buffer

DmaRegs.CH1.MODE.bit.CHINTE = 0; // Disable channel interrupt
DmaRegs.CH1.MODE.bit.ONESHOT = 0; // One shot mode disabled
DmaRegs.CH1.MODE.bit.CONTINUOUS = 1; // Continuous mode enabled
DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_TRIGGER_SOFTWARE;// DMA_ADCBINT3; // Peripheral interrupt source
DmaRegs.CH1.MODE.bit.PERINTE = 1; // Peripheral interrupt enable
DmaRegs.DEBUGCTRL.bit.FREE = 1;
DmaRegs.CH1.CONTROL.bit.RUN = 1;

DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)adcBuffer_src; // Source address
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)adcBuffer_dst; // Destination address
//DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint16)adcBuffer_dst;
//DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint16)adcBuffer_src;

__edis();

}