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TMS320F280039C: ADC conversion time

Kien
Expert 4126 points
Part Number: TMS320F280039C


Tool/software:

Hi Champs,

With F280049, I can see that the ADC interrupt happens right after the conversion is finished, ie. time since the ADC is triggered until the CLA task is called follows the equation:

SH = 12 Sysclock(100Mhz)  + ADCEOC 11 * 1/50MHz

However, with F280039C, similar settings and context, it looks like that there is a delay of few hundreds nanosecond added to all the conversions. Time since the ADC is triggered until the CLA task is called DOESN'T follow the equation:

SH = 10 Sysclock(120Mhz)  + ADCEOC 11 * 1/60MHz

Is there any clue for this?

Regards,

Kien Nguyen

  • 0
    TI__Genius 11081 points

    Kien,

    You should always use the ADC timings table in the TRM to determine the correct timings (ADC chapter, ADC Timings). The formula above is not necessarily accurate. If you're clocking ADC at 60MHz (PRESCALE=2), then the number of SYSCLK cycles from end of S+H to ADC interrupt pulse is 21 according to Table 16-9 (ADC Timings in 12-bit mode). This is fixed in the ADC digital wrapper logic.

    Please double-check your computations. Also, exactly how do you trigger the CLA task, and how are you measuring the ADC conversion time? If you do see extra latency beyond the timings specified in the TRM, it is definitely not coming from the ADC.

    Best regards,
    Ibukun