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TMS320F28388D: Cannot See OLUT Output

Ed Sanders
Genius 4085 points
Part Number: TMS320F28388D


Tool/software:

Greetings,

        I am porting CLB code from the 379D to the 388D.  I can load the logic config registers and observe the correct values when I read memory.  One of those values is an OLUT which has now been setup to always output a 1.  But when I read the CLB_DBG_OUT.OUTx, all outputs report 0.  I have checked the clocking to the CLB, and PCLKCR17 is 0xFF, which should be enabling all CLB clocks.  And the dividers are what I want them to be to run the CLB at 100 MHz.  Other than PCLKCR17, I can't find anything which would prevent a clock from getting to the tiles.

        So maybe I'm looking in the wrong place.  Is there something else I should be looking at to make the OLUT output appear?

Thank you,

Ed

  • 0
    Genius 4085 points

    OK.  This morning, I added some debug code to look at the register at the time when everything should be setup, and now I can see the expected value.  If I stop the processing at that time, I also see in the Registers tab.  But if I let it free run, I still do not see it.  Stay tuned...

    I think I see what is happening.  When CLB_LOAD_EN.GLOBAL_EN is 1, I can see it.  But when CLB_LOAD_EN.GLOBAL_EN is 0, everything in the tile is reset, including the OLUTs.  I am testing the error handling, and so GLOBAL_EN is 1 for a short period of time which prevented me from seeing it.

    But is it expected that the OLUTs will have their outputs go to zero when GLOBAL_EN is 0?

    Thank you,

    Ed

  • +1 in reply to Ed Sanders
    TI__Mastermind 28220 points

    Hi Ed,

    The register description for CLB_LOAD_EN.GLOBAL_EN in the TRM makes it clear that the CLB OUTLUTs will be low when CLB_LOAD_EN.GLOBAL_EN is zero:

    Let me know if you have additional questions.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    Genius 4085 points

    I missed that.

    Thank you Luke,

    Ed