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TMS320F28377S: Power sequencing

Viktorija Cecil
Mastermind 18501 points
Part Number: TMS320F28377S


Tool/software:

Team, 

Can you please help answer my customer's power sequencing questions?

  1.  In the datasheet specifies the following "VDDOSC and VDD must be powered on and off at the same time. VDDOSC should not be powered on when VDD is off. For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2837xS Real-Time MCUs Silicon Errata." 
    1. What is meant by "on" and "off" does this refer to the minimum recommended operating conditions on page 50?  I.e. VDDOSC should be below 3.14 as long as VDD is below 1.14V. 
    2. What is meant by "same time" are we talking about miliseconds, microseconds, nanoseconds or something faster between VDD crossing 1.14V and VDDOSC crossing 3.14V? 
    3. Or does this just mean that the enable pin for the 3.3V and 1.2V regulator should be from the same source and both regulators need to meet the ramp rate spec of between 330 and 10^5 V/s? 
      1. If so, do they both have to ramp at the same rate, or can they ramp at different rates that meet ramp rate spec?  This will help to mee the following requirement "The internal VREG is not supported. The VREGENZ pin must be tied to VDDIO and an external source used to supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO" as VDDIO and VDDOSC are powered by the same supply.
  2. We are planning to implement external voltage supervisors to monitor the 3.3V and 1.2V rail and trip when they are outside the recommended operating range (3.14-3.46 and 1.14-1.26), if they are outside this range the voltage supervisors will pull the XRS bar pin low with an open drain output.
    1. Will the XRS pin be guaranteed to respond and reset the device if any of the rails are outside the recommended operating range?

Thanks

Viktorija

  • 0
    TI__Expert 7100 points

    Hi Viktorija,

    Thanks for your patience.

    here are answer to your questions:

    1)

    a. yes

    b. it means the ramp rate of both VDD and VDDOSC follow the requirement given in "6.9.1.4.1 Supply Ramp Rate", and during the ramp, VDD should be kept no more than 0.3 V above VDDOSC. 

    c. yes, both regulators need to meet the ramp rate spec of between 330 and 10^5 V/s. They can ramp at different value, but VDD should be kept no more than 0.3 V above VDDOSC during the ramp. 

    2)

    a. yes

    Regards,

    Hadi