TMS320F28379D: Updating CLB counter Match1/2_ref value in real time ?

Hi Luke,

Yes, I had referred to that example. Just add the configuration in HLC program 0.

Then, load new period and duty cycle value in HLC Registers with driverAPI CLB_setHLCRegisters(CLB1_BASE, periodValue, dutyValue, 0, 0);

It seems that I could dynamically upload the counter match value. Would you kindly confirm the configuration is correct ?

One more ask on the example, the default counter match Match Reference 1 is 300, the PWM period is supposed to be 3us (1/100M *300) as CLB Tool User's Guide (SPRUIR8B) Figure 4-1. Example 3: Generated PWM Waveform shown, why the final captured by LA the period is 6us, two times of the configuration from default counter 0 Match Reference 1 ? Is there a configuration in GUI to double the counter ?

Thanks and regards,

Johnny

Hi Johnny,

I believe this configuration is correct.

Could you not just double the counter match value in your .c code? You could also slow down the frequency at which the counter updates by modifying the CLB clock settings.

Thank you,

Luke

Hi Luke,

The question on the counter match value, in TRM it shows that this output goes high whenever the counter register is equal to the MATCH1 REF input register, and also in CLB Tool User's Guide, it tells in this example, the period is 300 CLBCLK cycles (3 µs). 

 (SPRUIR8B)

 (example default configuration)

How come the real PWM output period is twice (6us) captured from LA, not as example shows that period is 300 CLBCLK cycles (3 µs) ? Where is the blue duration 3us coming from ? 

Upper channel : PWM output ; Lower channel : ISR toggle

Removing the line from loading the new duty cycle in CLB ISR.

Thanks and regards,

Johnny

Hi Johnny,

The CLB clock frequency varies depending on the device you're using and your clocking configuration. Can you verify the frequency of CLBCLK and determine if there is still an issue?

Thank you,

Luke