Other Parts Discussed in Thread: C2000WARE
Tool/software:
Hello,
I'm currently using the TMS320F2800157 C2000 MCU and cannot seem to get it to boot from flash. The issue exists both between my dev kit and the PCB we have manufactured. The boot pin configuration registers have not been touched in ROM, so the default pin routing should be selected of GPIO 24 and GPIO 32. Both pins are strapped high by either the switches on the dev kit or pull up resistors on the PCB. I've attached the linker file which is generated by SysCfg in code composer version 12.7.1.00001. I'm able to reliably flash and debug the MCU's on both boards with my XDS110 debugger, but neither MCU will boot after power cycling the board. Please let me know what other information is required to help resolve this issue.
Cheers,
-Alex
#ifdef generic_flash_lnk
MEMORY
{
RAMM0 : origin = 0x000128, length = 0x0002D8
RAMM1 : origin = 0x000400, length = 0x0003F8
RAMLS0 : origin = 0x008000, length = 0x002000
RAMLS1 : origin = 0x00A000, length = 0x001FF8
FLASH_BANK0_SEC_0_7 : origin = 0x080000, length = 0x002000
FLASH_BANK0_SEC_8_15 : origin = 0x082000, length = 0x002000
FLASH_BANK0_SEC_16_23 : origin = 0x084000, length = 0x002000
FLASH_BANK0_SEC_24_31 : origin = 0x086000, length = 0x002000
FLASH_BANK0_SEC_32_29 : origin = 0x088000, length = 0x002000
FLASH_BANK0_SEC_40_47 : origin = 0x08A000, length = 0x002000
FLASH_BANK0_SEC_48_55 : origin = 0x08C000, length = 0x002000
FLASH_BANK0_SEC_56_63 : origin = 0x08E000, length = 0x002000
FLASH_BANK0_SEC_64_71 : origin = 0x090000, length = 0x002000
FLASH_BANK0_SEC_72_79 : origin = 0x092000, length = 0x002000
FLASH_BANK0_SEC_80_87 : origin = 0x094000, length = 0x002000
FLASH_BANK0_SEC_88_95 : origin = 0x096000, length = 0x002000
FLASH_BANK0_SEC_96_103 : origin = 0x098000, length = 0x002000
FLASH_BANK0_SEC_104_111 : origin = 0x09A000, length = 0x002000
FLASH_BANK0_SEC_112_119 : origin = 0x09C000, length = 0x002000
FLASH_BANK0_SEC_120_127 : origin = 0x09E000, length = 0x001FF0
RESET : origin = 0x3FFFC0, length = 0x000002
}
SECTIONS
{
//
// C28x Sections
//
.reset : > RESET, TYPE = DSECT /* not used, */
codestart : > 0x080000
.text : >> FLASH_BANK0_SEC_104_111 | FLASH_BANK0_SEC_112_119 | FLASH_BANK0_SEC_120_127 | FLASH_BANK0_SEC_16_23 | FLASH_BANK0_SEC_24_31 | FLASH_BANK0_SEC_32_29 | FLASH_BANK0_SEC_40_47 | FLASH_BANK0_SEC_48_55 | FLASH_BANK0_SEC_56_63 | FLASH_BANK0_SEC_64_71 | FLASH_BANK0_SEC_72_79 | FLASH_BANK0_SEC_80_87 | FLASH_BANK0_SEC_88_95 | FLASH_BANK0_SEC_8_15 | FLASH_BANK0_SEC_96_103,
ALIGN(8)
.TI.ramfunc : LOAD > FLASH_BANK0_SEC_0_7,
RUN > RAMLS0,
TABLE(copyTable_ramfunc),
ALIGN(8)
.binit : > FLASH_BANK0_SEC_0_7,
ALIGN(8)
.ovly : > FLASH_BANK0_SEC_0_7,
ALIGN(8)
.cinit : > FLASH_BANK0_SEC_0_7,
ALIGN(8)
.stack : > RAMM1
.init_array : > FLASH_BANK0_SEC_0_7,
ALIGN(8)
.bss : > RAMLS0
.const : > FLASH_BANK0_SEC_32_29,
ALIGN(8)
.data : > RAMLS0
.switch : > FLASH_BANK0_SEC_0_7,
ALIGN(8)
.sysmem : > RAMLS0
//
// User Sections
//
FreeRTOS_Heap { *(.freertosHeap) } >> RAMLS0 | RAMLS1
FreeRTOS_Stack { *(.freertosStaticStack) } >> RAMLS0 | RAMLS1
dclfuncs { *(dclfuncs) } > RAMLS0,
ALIGN(2)
}
#endif
/*
//===========================================================================
// End of file.
//===========================================================================
*/
