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C28xx_CPU1: Error: (Error -1135 @ 0x8B25)

Part Number: TMS320F28379D
Other Parts Discussed in Thread: DRV8305, C2000WARE

Tool/software:

Hi,

I am using TMS320F28379D and DRV8305. I am using EPWM4, EPWM5 and EPWM6 (viz. GPIO6&7, GPIO8&9, GPIO10&11) to drive a 3 phase BLDC motor in open loop. However, I am getting the below error, whenever, I load and resume the program.

C28xx_CPU1: Error: (Error -1135 @ 0x8B25) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 12.7.0.00130)

and whenever, I comment out EPWM_setTimeBasePeriod for EPWM6, I am getting the modulated signal out from the controller for EPWM4 and EPWM5 and for EPWM6 a constant high signal.

What could be causing this?

        EPWM_setTimeBasePeriod(EPWM4_BASE, 2500);
        EPWM_setTimeBasePeriod(EPWM5_BASE, 2500);
//        EPWM_setTimeBasePeriod(EPWM6_BASE, 2500);

I have tested the JTAG connection and it passes, basic programs like GPIO toggling and other things are working fine.

  • I have gone through some other posts, however, unable to resolve the issue, screenshot of Test Connection:


    I have also tried to connect again, once I get the error and I am able to connect, however, in the console, I just get 
    C28xx_CPU1: GEL Output:
    Memory Map Initialization Complete

    I tried loading the program, the .out file however, after loading and again pressing "Resume" I am again getting the same error:

    I have tried the blinky program and it runs fine.

  • Hi

    Can you try scoping your JTAG signals when you lose connection? 

    The behavior that you're seeing usually indicates that your motor or power supply is causing so much EMI that JTAG becomes unusable. The fix would be do reduce the EMI or reroute JTAG signals.

    Best Regards,

    Ben Collier

  • Hi

    PFB JTAG Signals, TDO and TRST.

    After loading the program, we see this continuously:

    Green: TRST, Yellow: TDO

    On pressing resume all we see is high signal on both the channel.

  • Hi,

    Are you bandwidth limiting your oscilloscope? How do TCK and TMS look? 

    If you do a single capture for when you resume, do you not see any pulses on TCK or TDI? 

    Best Regards,

    Ben Collier

  • Hi Benjamin,

    There was some limitations on our scope that is why we probed TRST and TDO only, will probe all four JTAG signals and post. 

    Meanwhile, can you clarify somethings:

    1. Although, we are getting JTAG SI issues, I f i load the program directly on the FLASH, can i expect my program to run without any problems?
    2. We tried flashing the program, however, we got an error that .cinit size is too big for that FLASH, it was FLASHB. So, we made the modification in linker file and made it FLASHD and the code compiled. However, we could not see the output on the GPIO pins. FYI, when we are loading the program in RAM, the program works and we can see the output, so the code works(however, as mentioned earlier only if our GPIO115 pin is low). While flashing the program in FLASH, we also observed that the current consumption jumped from 0.18A to 0.7A.
  • Hi,

    • Although, we are getting JTAG SI issues, I f i load the program directly on the FLASH, can i expect my program to run without any problems?

    This will depend upon how bad the noise is.

    We tried flashing the program, however, we got an error that .cinit size is too big for that FLASH, it was FLASHB. So, we made the modification in linker file and made it FLASHD and the code compiled. However, we could not see the output on the GPIO pins. FYI, when we are loading the program in RAM, the program works and we can see the output, so the code works(however, as mentioned earlier only if our GPIO115 pin is low). While flashing the program in FLASH, we also observed that the current consumption jumped from 0.18A to 0.7A.

    You will need to change your codestart based upon where in FLASH the program is located. 

  • Hi

    1. We flashed on FLASHD and below is our linker command 

    MEMORY
    {
    PAGE 0 :  /* Program Memory */
              /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
              /* BEGIN is used for the "boot to Flash" bootloader mode   */
    
       BEGIN           	: origin = 0x080000, length = 0x000002
       RAMM0           	: origin = 0x000123, length = 0x0002DD
       RAMD0           	: origin = 0x00B000, length = 0x000800
       RAMLS0          	: origin = 0x008000, length = 0x000800
       RAMLS1          	: origin = 0x008800, length = 0x000800
       RAMLS2      		: origin = 0x009000, length = 0x000800
       RAMLS3      		: origin = 0x009800, length = 0x000800
       RAMLS4      		: origin = 0x00A000, length = 0x000800
       RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    
    //   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
       RESET           	: origin = 0x3FFFC0, length = 0x000002
    
       /* Flash sectors */
       FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
       FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
       FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
       FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
       FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
       FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
       FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
       FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
       FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
       FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
       FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
       FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
       FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
       FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */
    
    //   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
    PAGE 1 : /* Data Memory */
             /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */
    
       BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
       RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
    //   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
       RAMD1           : origin = 0x00B800, length = 0x000800
    
       RAMLS5      : origin = 0x00A800, length = 0x000800
    
       RAMGS0      : origin = 0x00C000, length = 0x001000
       RAMGS1      : origin = 0x00D000, length = 0x001000
       RAMGS2      : origin = 0x00E000, length = 0x001000
       RAMGS3      : origin = 0x00F000, length = 0x001000
       RAMGS4      : origin = 0x010000, length = 0x001000
       RAMGS5      : origin = 0x011000, length = 0x001000
       RAMGS6      : origin = 0x012000, length = 0x001000
       RAMGS7      : origin = 0x013000, length = 0x001000
       RAMGS8      : origin = 0x014000, length = 0x001000
       RAMGS9      : origin = 0x015000, length = 0x001000
       RAMGS10     : origin = 0x016000, length = 0x001000
    
    //   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */
    
    //   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    
       RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
       RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    
       CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
       CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
    }
    
    SECTIONS
    {
       /* Allocate program areas: */
       .cinit              : > FLASHD      PAGE = 0, ALIGN(8)
       .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
       codestart           : > BEGIN       PAGE = 0, ALIGN(8)
       /* Allocate uninitalized data sections: */S
       .stack              : > RAMM1       PAGE = 1
       .switch             : > FLASHB      PAGE = 0, ALIGN(8)
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */
    
    #if defined(__TI_EABI__)
       .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
       .bss                : > RAMLS5,       PAGE = 1
       .bss:output         : > RAMLS3,       PAGE = 0
       .bss:cio            : > RAMLS5,       PAGE = 1
       .data               : > RAMLS5,       PAGE = 1
       .sysmem             : > RAMLS5,       PAGE = 1
       /* Initalized sections go in Flash */
       .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
    #else
       .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
       .ebss               : >> RAMLS5 | RAMGS0 | RAMGS1,    PAGE = 1
       .esysmem            : > RAMLS5,       PAGE = 1
       .cio                : > RAMLS5,       PAGE = 1
       /* Initalized sections go in Flash */
       .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
    #endif
    
       Filter_RegsFile     : > RAMGS0,	   PAGE = 1
    
       SHARERAMGS0		: > RAMGS0,		PAGE = 1
       SHARERAMGS1		: > RAMGS1,		PAGE = 1
       SHARERAMGS2		: > RAMGS2,		PAGE = 1
       ramgs0           : > RAMGS0,     PAGE = 1
       ramgs1           : > RAMGS1,     PAGE = 1
    
    #ifdef __TI_COMPILER_VERSION__
        #if __TI_COMPILER_VERSION__ >= 15009000
            #if defined(__TI_EABI__)
                .TI.ramfunc : {} LOAD = FLASHD,
                                     RUN = RAMLS0,
                                     LOAD_START(RamfuncsLoadStart),
                                     LOAD_SIZE(RamfuncsLoadSize),
                                     LOAD_END(RamfuncsLoadEnd),
                                     RUN_START(RamfuncsRunStart),
                                     RUN_SIZE(RamfuncsRunSize),
                                     RUN_END(RamfuncsRunEnd),
                                     PAGE = 0, ALIGN(8)
            #else
                .TI.ramfunc : {} LOAD = FLASHD,
                                 RUN = RAMLS0,
                                 LOAD_START(_RamfuncsLoadStart),
                                 LOAD_SIZE(_RamfuncsLoadSize),
                                 LOAD_END(_RamfuncsLoadEnd),
                                 RUN_START(_RamfuncsRunStart),
                                 RUN_SIZE(_RamfuncsRunSize),
                                 RUN_END(_RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
            #endif
        #else
       ramfuncs            : LOAD = FLASHD,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    
    #endif
    
       /* The following section definitions are required when using the IPC API Drivers */
        GROUP : > CPU1TOCPU2RAM, PAGE = 1
        {
            PUTBUFFER
            PUTWRITEIDX
            GETREADIDX
        }
    
        GROUP : > CPU2TOCPU1RAM, PAGE = 1
        {
            GETBUFFER :    TYPE = DSECT
            GETWRITEIDX :  TYPE = DSECT
            PUTREADIDX :   TYPE = DSECT
        }
    
       /* The following section definition are for SDFM examples */
       Filter1_RegsFile : > RAMGS1,	PAGE = 1, fill=0x1111
       Filter2_RegsFile : > RAMGS2,	PAGE = 1, fill=0x2222
       Filter3_RegsFile : > RAMGS3,	PAGE = 1, fill=0x3333
       Filter4_RegsFile : > RAMGS4,	PAGE = 1, fill=0x4444
       Difference_RegsFile : >RAMGS5, 	PAGE = 1, fill=0x3333
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    

    Can you confirm if the above code is correct?

    2. On flashing my program, current goes from 0.178A to 0.695A and continue to increase and then stabilizes around 0.78A after 3-4 minute, Further, there appears to be a buzzing sound from the crystal oscillator. The output from the controller peripheral is as follows:

    Output of the GPIO which I enabled (this goes to EN_GATE pin of DRV8305):

    Output of the pins which generate EPWM:

    DRV8305 is connected to TMS320F28379D, Final output of the DRV8305 for U and V phase are similar:

    and output of w phase:


    However, when i power cycle, the current consumption comes to be 0.2A and the GPIO pin which is connected to the EN_GATE is continuously high and EPWM generated is also as expected, however, there is no output from the DRV8305.
    GPIO Pin connected to EN_GATE:

    All 3 EPWM Pins output are as expected:

    Also, few days back when I tried flashing the program on FLASH I did not get any JTAG break error, however, today, I am getting the below error. As I can see the output of EPWM as expected after power cycle, that does mean the program is flashed right?

    C28xx_CPU1: GEL Output:
    Memory Map Initialization Complete
    C28xx_CPU1: If erase/program (E/P) operation is being done on one core, the other core should not execute from shared-RAM (SR) as they are used for the E/P code. Also, CPU1 will be halted to determine SR ownership for the CPU which will run the Flash Plugin code, after which CPU1 will be set to run its application. User code execution from SR could commence after both flash banks are programmed.
    C28xx_CPU1: Error: (Error -1044 @ 0x0) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 12.7.0.00130)
    C28xx_CPU1: Trouble Halting Target CPU: (Error -1135 @ 0x80000) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 12.7.0.00130)
    C28xx_CPU1: Unable to determine target status after 20 attempts
    C28xx_CPU1: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging
    C28xx_CPU1: Error connecting to the target: (Error -1050 @ 0x0) Internal error: Invalid parameter passed to function. Restart the application. If error persists, please report the error. (Emulation package 12.7.0.00130)


    Further, what steps should I take to debug this?

  • Hi,

    1. It is very difficult for me to determine if your Linker CMD file will work correctly, I do not see any obvious problems.

    2. I'm not sure why your GPIOs are not working as expected after a power cycle, even though your PWM signals are. 

    Please try putting your device in wait boot mode when you are trying to flash new code. You're likely having problems with flashing while this program is running, since it is creating lots of noise. 

    Thanks,

    Ben Collier

  • Hi 

    1. I believe my linker CMD file is working correctly because after power cycle i can see the expected output from EPWM and GPIOs.

    2. 

    I'm not sure why your GPIOs are not working as expected after a power cycle, even though your PWM signals are. 

    A correction here, after power cycle, my PWM signals and GPIOs are working correctly. In my previous reply see the second last graph, which is continuously high, earlier I was unable to make it high.

    3. Now the problem is, there is no output from the DRV8305 and since my JTAG is not working properly, how do i read fault registers data from DRV8305 through SPI, because that will tell me why there is no output from DRV8305, right?

    4. I will try to put the device in wait mode and then flash and will update the result.

  • Hi Gautham,

    You are using DCSM correct? The wait boot mode solution only applies if security is being used.

    Thank you,

    Luke

  • Hi Luke,

    1. 

    "You are using DCSM correct? "

    How do i verify this?

    2. I have verified, just after I program controller output is not as expected, however, after power cycle the output of the controller is as expected, I can see PWM signals and GPIO pin which enables EN_GATE of DRV8305 is also high, as expected. However, there is no output from the DRV8305. Since, I am unable to connect using JTAG, how do i read the fault registers of DRV8305 through SPI, to know why am i not getting the output from DRV8305. Any help is appreciated.

  • Hi Gautham,

    My mistake, this issue has nothing to do with DCSM.

    To clarify, the issue now is that you need to read the values in the SPI registers being sent from the DRV8305 to the C2000 device, correct? Could you probe the SPI pins to check the messages being sent?

    Thank you,

    Luke

  • Hi Luke,

    As you can see from my previous posts, we are facing JTAG issues when we dump the program in CPU RAM so to circumvent this, I have started flashing the program directly on to the flash.

    Now after the program is running in the controller, we are unable to access JTAG probably due to noise issue, as highlighted by benjamin in his earlier post and hence, unable to view what is being read by the controller.

    Can you suggest me an alternative way to read the registers via SPI?  One thing I am currently trying is to read the SPI registers and then send those registers value by toggling GPIO pins. Fir example, i am reading registers at 0x01 of DRV8305 and then, the 16 bit value which is being read by controller, i am continuously sending it to one GPIO pins by toggling pins to identify what type of fault has occurred. Planning to do it for all the fault registers.

    This is a very crude method, is this approach right?

  • Hi,

    I was able to probe SPI lines on my custom board, FYI, I am using SPIC, as pine 122,123,124,and 125 are connected to SPI channels of DRV8305. I have two parts to my question.

    1. DRV8305 datasheet states MODE should be 1, I have set the same in my code. I observed that the MOSI signal does not look like it is set in MODE 1, however, my MISO signal is as per MODE 1. Can you please verify part of my SPI code and confirm the data which I am getting from DRV8305 is correct?

    #include "driverlib.h"
    #include "device.h"
    #include "board.h"
    #include "epwm.h"
    #include "math.h"
    //
    // Globals
    //
    
    #define DRV8305_FAULT_STATUS_1  0x8800 //1000 1000 0000 0000
    #define DRV8305_FAULT_STATUS_2  0x9000 //1001 0000 0000 0000
    #define DRV8305_FAULT_STATUS_3  0x9800 //1001 1000 0000 0000
    #define DRV8305_VDS_STATUS      0xA000 //1010 0000 0000 0000
    
    uint16_t faultStatus1;
    //
    // Some declarations
    
    //
    void main(void)
    {
    // Some device initialization codes
        initSPIC();
    
        for(;;)
        {
            faultStatus1 = readSPIRegister(DRV8305_VDS_STATUS);
            sendFaultStatus(faultStatus1);
        }
    }
    
    void initSPIC(void)
    {
        // Ensure SPI-C is disabled before configuration
        SPI_disableModule(SPIC_BASE);
    
        // Configure GPIOs for SPIC using predefined mappings
        GPIO_setPinConfig(GPIO_122_SPISIMOC); // Set GPIO122 as SPIC SIMO
        GPIO_setPinConfig(GPIO_123_SPISOMIC); // Set GPIO123 as SPIC SOMI
        GPIO_setPinConfig(GPIO_124_SPICLKC);  // Set GPIO124 as SPIC CLK
        GPIO_setPinConfig(GPIO_125_SPISTEC);  // Set GPIO125 as SPIC STE
    
        // Configure SPI in master mode
        SPI_setConfig(SPIC_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1, SPI_MODE_MASTER, 500000, 16);
        SPI_enableFIFO(SPIC_BASE);
        SPI_enableModule(SPIC_BASE);
    }
    
    uint16_t readSPIRegister(uint16_t address)
    {
        uint16_t receivedData;
    
        // Send the address to the DRV8305
        SPI_writeDataBlockingFIFO(SPIC_BASE, address);
    
        // Read the received data
        receivedData = SPI_readDataBlockingFIFO(SPIC_BASE);
    
        return receivedData;
    }
    
    
    
    void sendFaultStatus(uint16_t faultStatus)
    {
        GPIO_writePin(119, (faultStatus & 0x01));  // Example: toggle based on LSB
    }
    
    
    //My interrupt code for generating pwm
    
    
    

    Below are the SCLK, MOSI and MISO output as probed using oscilloscope. Note: I have access to only 2 probes at a time currently.

    Fault Register 0x01 (DRV8305_FAULT_STATUS_1) 

    Yellow: Clock, Orange: MOSI                                                           Yellow: Clock, Orange: MISO

    Fault Register 0x02 (DRV8305_FAULT_STATUS_2) 

    Yellow: Clock, Orange: MOSI                                                          Yellow: Clock, Orange: MISO

    Fault Register 0x03 (DRV8305_FAULT_STATUS_3) 

    Yellow: Clock, Orange: MOSI                                                          Yellow: Clock, Orange: MISO

    Fault Register 0x04 (DRV8305_VDS_STATUS) 

    Yellow: Clock, Orange: MOSI                                                          Yellow: Clock, Orange: MISO

    2. If the above SPI reads are correct then,

    We getting fault in 0x03, which is IC Fault register and the error that we are getting are:

    • Watchdog fault
    • Overtemperature fault
    • VREG undervoltage fault
    • High-side charge pump undervoltage 2 fault

    Please confirm if that is the case, and how do i resolve this?

    Further, why for 0x01, reserved bit is high, is that normal? because for 0x02 reserved bit is not high

  • Hi,

    Some more information:

    As stated above, for channel 2, on commenting out "EPWM_setTimeBasePeriod(EPWM6_BASE, 2500);" U and V phase were working

    and whenever, I comment out EPWM_setTimeBasePeriod for EPWM6, I am getting the modulated signal out from the controller for EPWM4 and EPWM5 and for EPWM6 a constant high signal.

    We have now discovered that on commenting out "EPWM_setTimeBasePeriod(EPWM1_BASE, 2500);"  U phase is high continuously and V and W phase were working as expected, however, on setting EPWM_setTimeBasePeriod(EPWM1_BASE, 2500); we are getting fault in DRV8305, whose fault registers are as above. (If it is correct)

    This is for your information.

  • Gautham,

    Why would you ever want to comment out the code that sets the TBPRD for the EPWMs? What is your desired output on EPWM1?

    Thank you,

    Luke

  • Hi Luke, 

    We discovered this accidentally that commenting out TBRD for the EPWM6 and EPWM1 for channel and 2 and 1 respectively, we are getting output from the DRV in other 2 channels i.e V and W phase in channel 1 and U and V phase in channel 2. This was only for your information  that, by doing so DRV was not giving any fault and we were getting output from.

    To test our custom board, we are trying to run an open loop program, wherein, output on ePWM1 will be a sinusoidal waveform, modulated by the PWM signal.

  • Hi,

    Update: Since we were getting  VCPH_UVLO2 fault among other faults, we probed VREG and PVDD and we are getting behaviour as shown in graph. This happens only when epwm1/epwm6 is active. 

    While operating other epwm we do not see this transient behaviour when EN_GATE is enabled.

    PVDDD probed near a 0 ohm resistor close to DRV, when probing the 28V direct supply, the drop is less

    VREG

    This is the cause for VCPH_UVLO2 fault? what about other faults that we are observing?

    How do we resolve this? Should we place just a 10 uF capacitor between PVDD and ground, would that be enough? How else should we debug this?

    PS:
    We have already have a 4.7uF capacitor

  • Hi Gautham,

    To clarify, there is no issue with the EPWM outputs, but when EPWM1 and EPWM6 are running, you seem to get noise in the system that is preventing JTAG connection. Is this correct?

    Thank you,

    Luke

  • Hi Luke,

    "To clarify, there is no issue with the EPWM outputs, but when EPWM1 and EPWM6 are running, you seem to get noise in the system that is preventing JTAG connection. Is this correct?"

    Yes, you are correct. 

    Since I was getting JTAG break and unable to run the program whenever I was using EPWM1 and EPWM6, I dumped the program directly on the flash. On doing so, I can see that controller output is alright and EPWM waveforms are as expected on EPWM1, however, no output in DRV8305. nfault is Low.

  • Hi,

    Update: We identified an issue, a 0 ohm resistance was missing for SH_A, we populated the same and now we are getting output from the DRV in all three channels.

    Question:

    We are still not sure if our SPI read is correct or not, our SPI read tells us there is a fault as some bits of 0x03 register are high. Can you please confirm from the above SPI signals probed if the behaviour of MOSI is correct? It does not look like SPI mode1 behaviour, as clock falling edge is aligned with the falling edge of the MOSI bit.

    We are using standard SPI libraries

    #include "driverlib.h"
    #include "device.h"
    #include "board.h"
    #include "epwm.h"
    #include "math.h"
    #include "spi.h"
    //
    // Globals
    //
    
    #define DRV8305_FAULT_STATUS_1  0x8800 //1000 1000 0000 0000
    #define DRV8305_FAULT_STATUS_2  0x9000 //1001 0000 0000 0000
    #define DRV8305_FAULT_STATUS_3  0x9800 //1001 1000 0000 0000
    #define DRV8305_VDS_STATUS      0xA000 //1010 0000 0000 0000
    
    uint16_t faultStatus1;
    //
    // Some declarations
    
    //
    void main(void)
    {
    // Some device initialization codes
        initSPIC();
    
        for(;;)
        {
            faultStatus1 = readSPIRegister(DRV8305_VDS_STATUS);
            sendFaultStatus(faultStatus1);
        }
    }
    
    void initSPIC(void)
    {
        // Ensure SPI-C is disabled before configuration
        SPI_disableModule(SPIC_BASE);
    
        // Configure GPIOs for SPIC using predefined mappings
        GPIO_setPinConfig(GPIO_122_SPISIMOC); // Set GPIO122 as SPIC SIMO
        GPIO_setPinConfig(GPIO_123_SPISOMIC); // Set GPIO123 as SPIC SOMI
        GPIO_setPinConfig(GPIO_124_SPICLKC);  // Set GPIO124 as SPIC CLK
        GPIO_setPinConfig(GPIO_125_SPISTEC);  // Set GPIO125 as SPIC STE
    
        // Configure SPI in master mode
        SPI_setConfig(SPIC_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1, SPI_MODE_MASTER, 500000, 16);
        SPI_enableFIFO(SPIC_BASE);
        SPI_enableModule(SPIC_BASE);
    }
    
    uint16_t readSPIRegister(uint16_t address)
    {
        uint16_t receivedData;
    
        // Send the address to the DRV8305
        SPI_writeDataBlockingFIFO(SPIC_BASE, address);
    
        // Read the received data
        receivedData = SPI_readDataBlockingFIFO(SPIC_BASE);
    
        return receivedData;
    }
    
    
    
    void sendFaultStatus(uint16_t faultStatus)
    {
        GPIO_writePin(119, (faultStatus & 0x01));  // Example: toggle based on LSB
    }
    
    
    //My interrupt code for generating pwm

  • Hi Gautham,

    I will get back to you in 1-2 days regarding your question.

    Aishwarya

  • Gautham,

    Taking a quick look at the DRV805 DS, it looks the SPI mode listed there is equivalent of the F28379xD SPI controller / master mode with polarity=0 and phase=0. Please do double check. Have you also looked at the C2000Ware examples as they showcase how to configure the SPI? If not, please do.

    Best Regards,

    Aishwarya

  • Hi ,

    Please have a look at the below snippet of code, this is configuring it to Mode 1, right?

        SPI_setConfig(SPIC_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA1, SPI_MODE_MASTER, 500000, 16);

  • Gautham,

    Different products refer to different mode numbering, so it's important to match the timing diagrams. Looks like you would need to do:

     SPI_setConfig(SPIC_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0, SPI_MODE_MASTER, 500000, 16);

    Aishwarya

  • Hi Aishwarya,

    We are using DRV8305, it states that we need to operate it in mode1.

  • Hi Gautham,

    Aishwarya is currently out of office so please expect some delay in her response.

    Best Regards,

    Delaney

  • Hi,

    Apologies for the delay. You are correct, please disregard my previous comment. Can you please confirm that the SPI is both reading and writing at the same time and that everything else is working as expected except for this one-time fault? 

    Best Regards,

    Aishwarya

  • Gautham,

    Checking in to see if this issue has been resolved and/or there are any pending questions?

    Best Regards,

    Aishwarya