Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE
Tool/software:
Hello Community,
For a particular project we need to use both CPUs, CM (with EtherCAT) and CLB. Since we need to use ePWM @200MHz, we are forced to configure the CLB so that it runs asynchronous respect to SYSCLK.
So, through the driverlib we managed to configure the DSP so that SYSCLK is 200MHz and AUXCLK is 100MHz, meaning that CPUs run @200MHz whilst CM and CLB run @100MHz.
It appears to work fine so far, but there are some aspects we would like to be sure of:
- Is there any known problem slowing down the clock of the CM from 125MHz to 100MHz? And consequently running ECAT @100MHz?
- Do we need to pay particular attention while running CLB half the frequency of the CPUs? For example, if we wanted to use a Memory Mapped GPREG BIT as an input for the CLBx, do we run the risk of missing information?
- There might be a small issue in the driverlib. If you use the function
static inline void
SysCtl_setCLBClkDivider(SysCtl_CLBClkDivider divider, SysCtl_CLBTClkDivider tdivider)
{
EALLOW;
//
// Clear the CLB clk configurations
//
HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) =
(HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) &
~(SYSCTL_CLBCLKCTL_CLBCLKDIV_M |
SYSCTL_CLBCLKCTL_TILECLKDIV));
//
// Set the clock dividers
//
HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) |=
((uint32_t)divider << SYSCTL_CLBCLKCTL_CLBCLKDIV_S) |
((uint32_t)tdivider << SYSCTL_CLBCLKCTL_TILECLKDIV_S);
EDIS;
}
after having set the the CLB as asynchronous via the SysCtl_CLBClkConfig(SysCtl_CLBInst inst, SysCtl_CLBClkm config), the asynchronicity gets reset for all the CLBs. This is because of the macros:
#define SYSCTL_CLBCLKCTL_CLBCLKDIV_M 0x7U // CLB clock divider configuration.
#define SYSCTL_CLBCLKCTL_TILECLKDIV 0x10U // CLB Tile clock divider configuration.
Since they both are "U" and not "UL", when you do HWREG(CLKCFG_BASE + SYSCTL_O_CLBCLKCTL) & ~(SYSCTL_CLBCLKCTL_CLBCLKDIV_M | SYSCTL_CLBCLKCTL_TILECLKDIV), you actually erase also the first part of the 32bit register (where the asynchronicity is set). We found this after some time of apparently inexplicable clocking issues, so we now made a workaround, but it might be worth fixing this in the next C2000ware releases (unless you did already, we are now using 4.03 and 5.0).
Thank you in advance and regards,
Michel
