C2000WARE: Issue with SCI-D Port RX Interrupt on TSM320F28377s

Hi,

sj kim said:

PieCtrlRegs.PIEIER8.bit.INTx5 = 1; // Enable SCID RX interrupt

Here, you are enabling interrupt 8.5, which is mapped to SCI-C RX int. For SCI-D RX int, you would need to enable interrupt 8.7

Let me know if you have any other issues.

Thanks,

Arnav

Thank you for your response.
I have made the suggested modifications, but the RX interrupt on the SCI-D port is still not being triggered.
Could you please advise if there are any additional changes or configurations that I need to make?

Thank you for your help.

Best regards.
sjkim

#include "F28x_Project.h"

#define CPU_FREQ 60E6
#define LSPCLK_FREQ CPU_FREQ/4
#define SCI_FREQ 115200//100E3
#define SCI_PRD ((LSPCLK_FREQ/(SCI_FREQ*8))-1)

interrupt void scidRxFifoIsr(void);
void scid_fifo_init(void);

volatile bool g_bGotRx = false;


void setScidRxinitInterrupts(void)
{
EALLOW;
PieVectTable.SCID_RX_INT = &scidRxFifoIsr;
EDIS;

PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER8.bit.INTx7 = 1; // Enable SCI-D RX interrupt <--- modified
//IER |= M_INT8; // Enable CPU INT8
IER |= PIEACK_GROUP8; // Enable CP
}

void main(void)
{
char ReceivedChar;

InitSysCtrl();
InitGpio();
DINT;
InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

EALLOW;

GPIO_SetupPinMux(47, GPIO_MUX_CPU1, 15); // SCI-d RX Pin: GPIO47
GPIO_SetupPinOptions(47, GPIO_INPUT, (GPIO_PUSHPULL | GPIO_SYNC));
GPIO_SetupPinMux(46, GPIO_MUX_CPU1, 15); // SCI-d TX Pin: GPIO46
GPIO_SetupPinOptions(47, GPIO_OUTPUT, GPIO_PUSHPULL);
EDIS;

scid_fifo_init(); // Init SCI-D

setScidRxinitInterrupts();

EINT;
ERTM;

while(1)
{
if(g_bGotRx) {
printfPort('D',(char*)"Got()\r\n");
g_bGotRx = false;
}
if(ScidRegs.SCIFFRX.bit.RXFFST)
{
ReceivedChar = ScidRegs.SCIRXBUF.all;
printfPort('D',"%02x\r\n", ReceivedChar);
}
}
}

interrupt void scidRxFifoIsr(void)
{
uint16_t receivedChar;
receivedChar = ScidRegs.SCIRXBUF.all;
ScidRegs.SCITXBUF.all = receivedChar;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

g_bGotRx = true;
printfPort('D',(char*)"receivedCha\r\n");
}

void scid_fifo_init()
{
ScidRegs.SCICCR.all = 0x0007;
ScidRegs.SCICTL1.all = 0x0003;
ScidRegs.SCICTL2.bit.TXINTENA = 1;
ScidRegs.SCICTL2.bit.RXBKINTENA = 1;

ScidRegs.SCIHBAUD.all = 0x0000;
ScidRegs.SCILBAUD.all = SCI_PRD;

ScidRegs.SCICTL1.all = 0x0023;

ScidRegs.SCIFFTX.all = 0xC022; //TX FIFO
ScidRegs.SCIFFRX.all = 0x0022; //RX FIFI
ScidRegs.SCIFFCT.all = 0x00;

ScidRegs.SCICTL1.all = 0x0023;
ScidRegs.SCIFFRX.bit.RXFIFORESET = 1;
}

Hi,

Within your RX ISR, you would need to clear the RX Interrupt and Overflow flag, otherwise further RX interrupts will not be triggered after the 1st one is serviced. You can refer to the example at [C2000WARE]\device_support\f2837xs\examples\cpu1\sci_loopback_interrupts\cpu01

If you are still not seeing any RX interrupts triggered, I suggest probing the incoming data to make sure everything is in order. If the above loopback example works as expected for SCID, it may be an issue with the configured GPIO pins.

Thanks,

Arnav

Hi.

Thank you for your response.
I have made the modifications as you suggested, but the interrupt is still not triggering.
Could you please advise on what additional steps I can take to resolve this issue?

Thank you for your assistance.

Best regards,

sjkim

Hi,

The RX side configurations look to be fine; you can confirm this by enabling loopback and adding a TX ISR to send data & verify the transmissions. The issue is most likely from the TX side. How is data being transmitted to the device?  Are you able to scope out the TX lines to make sure the transmitted data is correct?

If the scoped data is correct, can you inspect the SCIRXBUF and SCIFFRX.RXFFST to check if data is being received in the SCI module? If this fails, then it is likely an issue with the GPIO connections/pins themselves. Note that you have configured the RX&TX FIFO levels to 2, so the RX interrupt will be triggered when the RX FIFO has 2 or more bytes.

Thanks,

Arnav

HI.

Thanks you your response.

I am encountering an issue where interrupts are not being triggered when sending characters through Tera Term.
However, the characters are being received in ScidRegs.SCIRXBUF.all.
For example, when sending “123” from Tera Term, the received data is as follows:

<RxD> 31
<RxD> 32
<RxD> 33
<RxD> 0d

Please refer to the code below for further details.

Thank you for your assistance.

Best regards,
sjkim

interrupt void scidRxFifoIsr(void)
{
   uint16_t receivedChar;
   receivedChar = ScidRegs.SCIRXBUF.all;
   ScidRegs.SCITXBUF.all = receivedChar;
   PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

   ScidRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
   ScidRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag

   PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack

   g_bGotRx = true;
}

void main()
{
   while(1)
   {
      if(g_bGotRx) {
         printfPort('D',(char*)"Got()\r\n");
         g_bGotRx = false;
     }
     if(ScidRegs.SCIFFRX.bit.RXFFST)
     {
        ReceivedChar = ScidRegs.SCIRXBUF.all;
        printfPort('D',"<RxD>%02x\r\n", ReceivedChar);
     }
  }
}

Hi

I have been waiting for a response regarding this problem and would greatly appreciate any hints or solutions you could provide to resolve this issue.

Thank you for your time and assistance.

Best regards,

sjkim

Hi,

You are currently reading the SCI RXBUFFER from within the interrupt, as well as in the main loop. Can you try removing the read in main(), and reading the 2 characters directly from the interrupt. This extra read in main may be emptying the FIFO before it ever reaches 2 elements, thus leading to interrupt not being triggered.

Thanks,

Arnav

Hello

Thank you for your previous response.

I followed your instructions, but the Rx interrupt is still not being triggered at all.
It has never occurred.
I am attaching my full source code below for your reference.

Thank you in advance for your help.

Best regards,

sjkim

---------------------------------------
#include "F28x_Project.h"

#define CPU_FREQ 60E6
#define LSPCLK_FREQ CPU_FREQ/4
#define SCI_FREQ 115200//100E3
#define SCI_PRD ((LSPCLK_FREQ/(SCI_FREQ*8))-1)

interrupt void scidRxFifoIsr(void);
void scid_fifo_init(void);

void initInterrupts(void)
{
EALLOW;
PieVectTable.SCID_RX_INT = &scidRxFifoIsr;
EDIS;

PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER8.bit.INTx7 = 1; // Enable SCI-D RX interrupt

//IER |= M_INT8; // Enable CPU INT8
IER |= PIEACK_GROUP8; // Enable CP
}

volatile bool g_bGotRx = false;

void main(void)
{
char ReceivedChar;

InitSysCtrl();
InitGpio();
DINT;
InitPieCtrl();

IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

EALLOW; // This is needed to write to EALLOW protected registers

GPIO_SetupPinMux(47, GPIO_MUX_CPU1, 15);
GPIO_SetupPinOptions(47, GPIO_INPUT, (GPIO_PUSHPULL | GPIO_SYNC));
GPIO_SetupPinMux(46, GPIO_MUX_CPU1, 15);
GPIO_SetupPinOptions(47, GPIO_OUTPUT, GPIO_PUSHPULL);
EDIS; // This is needed to disable write to EALLOW protected registers

scid_fifo_init(); // Init SCI-D

initInterrupts(); // 인터럽트 설정

EINT;
ERTM;

if (bInit() != true)
{
printfPort('D', (char*)"<Error>bInit()\r\n");
}
printfPort('D',(char*)"bInit()\r\n");

while(1)
{
if(g_bGotRx) {
printfPort('D',(char*)"Got()\r\n");
g_bGotRx = false;
}
#if 0
if(ScidRegs.SCIFFRX.bit.RXFFST)
{
ReceivedChar = ScidRegs.SCIRXBUF.all;
printfPort('D',"<RxD>%02x\r\n", ReceivedChar);
}
#endif
}
}

interrupt void scidRxFifoIsr(void)
{
uint16_t receivedChar;

#if 0
receivedChar = ScidRegs.SCIRXBUF.all;
ScidRegs.SCITXBUF.all = receivedChar;
#endif
PieCtrlRegs.PIEACK.all = PIEACK_GROUP8;

#if 1
receivedChar = ScidRegs.SCIRXBUF.all;
printfPort('D',"<RxD>%02x\r\n", receivedChar);
#endif

ScidRegs.SCIFFRX.bit.RXFFOVRCLR=1; // Clear Overflow flag
ScidRegs.SCIFFRX.bit.RXFFINTCLR=1; // Clear Interrupt flag

PieCtrlRegs.PIEACK.all|=0x100; // Issue PIE ack

g_bGotRx = true;
}

void scid_fifo_init()
{
ScidRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback
// No parity, 8 char bits,
// async mode, idle-line protocol
ScidRegs.SCICTL1.all = 0x0003; // Enable TX, RX, internal SCICLK,
// Disable RX ERR, SLEEP, TXWAKE
ScidRegs.SCICTL2.bit.TXINTENA = 1;
//ScidRegs.SCICTL2.bit.RXBKINTENA = 1;

// SCI-D at 100000 baud
ScidRegs.SCIHBAUD.all = 0x0000;
ScidRegs.SCILBAUD.all = SCI_PRD;

ScidRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset

ScidRegs.SCIFFTX.all = 0xC022; //TX FIFO
ScidRegs.SCIFFRX.all = 0x0022; //RX FIFI
ScidRegs.SCIFFCT.all = 0x00;

ScidRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset
//ScidRegs.SCIFFTX.bit.TXFIFORESET = 1;
ScidRegs.SCIFFRX.bit.RXFIFORESET = 1;
}

Hello

I am writing to inquire about when I might receive a response regarding my issue. Upon uploading my code to the TSM320F28377S, I quickly realized that the UART Rx interrupt does not occur. Despite thoroughly reviewing the datasheet, I am unable to identify the problem.

I am looking forward to your assistance.

Thank you for your support.

Best regards,

sjkim

Hi,

Apologies for the delay.

sj kim said:

//ScidRegs.SCICTL2.bit.RXBKINTENA = 1;

You seem to have commented out the RX interrupt enable for the SCI module. Is it working with this bit enabled? Your SCID - SCIFFRX register should look something like this after initialization is complete (apart from the addresses).

Also, you only have to perform PIE interrupt acknowledge one time in the ISR, this can be done at the end.

Apart from this, your settings look correct. Are you disabling interrupts in any other part of your application? Also, can you try with another SCI instance in a different PIE Group (SCI A or B) to check if the issue is with SCI module, or if interrupts are being blocked by some other source

Thanks,

Arnav