Part Number: TMS320F28388D
Tool/software:
Hello, Mr. Expert,
I am having some problems with the F28388D board when communicating between cores between CPU1 and CM.
In the communication between the cores, I allocate 1000 bytes buffer for each core to send data.
CM:
#define IPC_BUFFERS_SIZE 250
#pragma DATA_SECTION(CMData, “READ_DATA_RAM”)
uint32_t CMData[IPC_BUFFERS_SIZE];
CPU1:
#define IPC_BUFFERS_SIZE 500
#pragma DATA_SECTION(CPU1Data, “MSGRAM_CPU_TO_CM”)
uint32_t CPU1Data[IPC_BUFFERS_SIZE];
I am communicating between cores, but the buffer I allocated in CPU1 breaks my SCI communication because the buffer size is large and when I create a dynamic array with malloc, it gives an Interrupt_IllegalOperationHandler() error, but when I make IPC_BUFFER_SIZE 250 in CPU1, only SCI communication is improved, but it continues to give errors due to malloc.
I know that the problem is related to the memory layout in the cmd file but I can't find a solution.
Can you support me on this issue.
/*
*CPU1 FLASH CMD FILE
*/
MEMORY
{
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B1, length = 0x00024F
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/*
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
*/
RAMLS0 : origin = 0x008000, length = 0x001800
RAMLSxDxGSx : origin = 0x009800, length = 0x006200
RAMGSx : origin = 0x010000, length = 0x00CFF8
/*
RAMD0 : origin = 0x00C000, length = 0x000800
RAMD1 : origin = 0x00C800, length = 0x000800
RAMGS0 : origin = 0x00D000, length = 0x001000
RAMGS1 : origin = 0x00E000, length = 0x001000
RAMGS2 : origin = 0x00F000, length = 0x001000
RAMGS3 : origin = 0x010000, length = 0x001000
RAMGS4 : origin = 0x011000, length = 0x001000
RAMGS5 : origin = 0x012000, length = 0x001000
RAMGS6 : origin = 0x013000, length = 0x001000
RAMGS7 : origin = 0x014000, length = 0x001000
RAMGS8 : origin = 0x015000, length = 0x001000
RAMGS9 : origin = 0x016000, length = 0x001000
RAMGS10 : origin = 0x017000, length = 0x001000
RAMGS11 : origin = 0x018000, length = 0x001000
RAMGS12 : origin = 0x019000, length = 0x001000
RAMGS13 : origin = 0x01A000, length = 0x001000
RAMGS14 : origin = 0x01B000, length = 0x001000
RAMGS15 : origin = 0x01C000, length = 0x000FF8
*/
// RAMGS15_RSVD : origin = 0x01CFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
/* Flash sectors */
FLASH0 : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASH13 : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */
// FLASH13_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000800
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000800
CPUTOCMRAM : origin = 0x039000, length = 0x000800
CMTOCPURAM : origin = 0x038000, length = 0x000800
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
}
SECTIONS
{
codestart : > BEGIN, ALIGN(8)
.text : >> FLASH1 | FLASH2 | FLASH3 | FLASH4, ALIGN(8)
.cinit : > FLASH4, ALIGN(8)
.switch : > FLASH1, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMLSxDxGSx
/* IMPORTANT: The FreeRTOS statically allocated stack should be allocated to this section only */
.freertosStaticStack : >> RAMM1 | RAMM0
/* IMPORTANT: The FreeRTOS heap should be allocated to this section only as the C28x stack
memory can be allocated in the lower 64k RAM memory only. */
.freertosHeap : > RAMLSxDxGSx
#if defined(__TI_EABI__)
.init_array : > FLASH1, ALIGN(8)
.bss : > RAMGSx
.bss:output : > RAMGSx
.bss:cio : > RAMM0
.data : > RAMGSx
.sysmem : > RAMLS0
/* Initalized sections go in Flash */
.const : > FLASH5, ALIGN(8)
#else
.pinit : > FLASH1, ALIGN(8)
.ebss : > RAMGSx
.esysmem : > RAMLSxDxGSx
.cio : > RAMM0
/* Initalized sections go in Flash */
.econst : >> FLASH4 | FLASH5, ALIGN(8)
#endif
/*
ramgs0 : > RAMGS0, type=NOINIT
ramgs1 : > RAMGS1, type=NOINIT
*/
ramm0 : > RAMM0, type=NOINIT
ramm1 : > RAMM1, type=NOINIT
MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
MSGRAM_CPU_TO_CM : > CPUTOCMRAM, type=NOINIT
MSGRAM_CM_TO_CPU : > CMTOCPURAM, type=NOINIT
/* The following section definition are for SDFM examples */
/*
Filter_RegsFile : > RAMGS0
Filter1_RegsFile : > RAMGS1, fill=0x1111
Filter2_RegsFile : > RAMGS2, fill=0x2222
Filter3_RegsFile : > RAMGS3, fill=0x3333
Filter4_RegsFile : > RAMGS4, fill=0x4444
Difference_RegsFile : >RAMGS5, fill=0x3333
*/
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASH3,
RUN = RAMGSx,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASH3,
RUN = RAMGSx,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
ALIGN(8)
#endif
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
/*
*CM FLASH CMD FILE
*/
MEMORY
{
/* Flash sectors */
CMBANK0_RESETISR : origin = 0x00200000, length = 0x00000008 /* Boot to Flash Entry Point */
CMBANK0_SECTOR0 : origin = 0x00200008, length = 0x00003FF7
CMBANK0_SECTOR1 : origin = 0x00204000, length = 0x00004000
CMBANK0_SECTOR2 : origin = 0x00208000, length = 0x00004000
CMBANK0_SECTOR3 : origin = 0x0020C000, length = 0x00004000
CMBANK0_SECTOR4 : origin = 0x00210000, length = 0x00010000
CMBANK0_SECTOR5 : origin = 0x00220000, length = 0x00010000
CMBANK0_SECTOR6 : origin = 0x00230000, length = 0x00010000
CMBANK0_SECTOR7 : origin = 0x00240000, length = 0x00010000
CMBANK0_SECTOR8 : origin = 0x00250000, length = 0x00010000
CMBANK0_SECTOR9 : origin = 0x00260000, length = 0x00010000
CMBANK0_SECTOR10 : origin = 0x00270000, length = 0x00004000
CMBANK0_SECTOR11 : origin = 0x00274000, length = 0x00004000
CMBANK0_SECTOR12 : origin = 0x00278000, length = 0x00004000
CMBANK0_SECTOR13 : origin = 0x0027C000, length = 0x00004000
C1RAM : origin = 0x1FFFC000, length = 0x00001FFF
C0RAM : origin = 0x1FFFE000, length = 0x00001FFF
BOOT_RSVD : origin = 0x20000000, length = 0x00000800 /* Part of S0, BOOT rom will use this for stack */
SRAM : origin = 0x20000800, length = 0x0000F7FF
E0RAM : origin = 0x20010000, length = 0x00003FFF
CPU1TOCMMSGRAM0 : origin = 0x20080000, length = 0x00000800
CPU1TOCMMSGRAM1 : origin = 0x20080800, length = 0x00000800
CMTOCPU1MSGRAM0 : origin = 0x20082000, length = 0x00000800
CMTOCPU1MSGRAM1 : origin = 0x20082800, length = 0x00000800
CPU2TOCMMSGRAM0 : origin = 0x20084000, length = 0x00000800
CPU2TOCMMSGRAM1 : origin = 0x20084800, length = 0x00000800
CMTOCPU2MSGRAM0 : origin = 0x20086000, length = 0x00000800
CMTOCPU2MSGRAM1 : origin = 0x20086800, length = 0x00000800
// CPU1TOCMMSGRAM0 : origin = 0x20080000, length = 0x00000800
// CPU1TOCMMSGRAM1 : origin = 0x20080800, length = 0x00000800
// CMTOCPU1MSGRAM0 : origin = 0x20082000, length = 0x00001000
// CMTOCPU1MSGRAM1 : origin = 0x20083000, length = 0x00001000
// CMTOCPU2MSGRAM0 : origin = 0x20086000, length = 0x00000800
// CMTOCPU2MSGRAM1 : origin = 0x20086800, length = 0x00000800
}
SECTIONS
{
.resetisr : > CMBANK0_RESETISR
.vftable : > CMBANK0_SECTOR0 /* Application placed vector table in Flash*/
.vtable : > SRAM /* Application placed vector table in RAM*/
.text : >> CMBANK0_SECTOR4
.cinit : > CMBANK0_SECTOR0
.pinit : >> CMBANK0_SECTOR0 | CMBANK0_SECTOR1
.switch : >> CMBANK0_SECTOR0 | CMBANK0_SECTOR1
.sysmem : > SRAM
.stack : > C1RAM
.ebss : > C1RAM
.econst : >> CMBANK0_SECTOR0 | CMBANK0_SECTOR1
.esysmem : > C1RAM
.data : > SRAM
.bss : > SRAM
.const : {} LOAD = CMBANK0_SECTOR0 | CMBANK0_SECTOR1 ,
RUN = SRAM,
LOAD_START(constLoadStart),
LOAD_SIZE(constLoadSize),
LOAD_END(constLoadEnd),
RUN_START(constRunStart),
RUN_SIZE(constRunSize),
RUN_END(constRunEnd)
MSGRAM_CM_TO_CPU1 : > CMTOCPU1MSGRAM0, type=NOINIT
MSGRAM_CM_TO_CPU2 : > CMTOCPU2MSGRAM0, type=NOINIT
MSGRAM_CPU1_TO_CM : > CPU1TOCMMSGRAM0, type=NOINIT
MSGRAM_CPU2_TO_CM : > CPU2TOCMMSGRAM0, type=NOINIT
READ_DATA_RAM : > CMTOCPU1MSGRAM0, type=NOINIT
// MSGRAM_CM_TO_CPU1 : > 0x20082000, type=NOINIT
// MSGRAM_CM_TO_CPU2 : > CMTOCPU2MSGRAM0, type=NOINIT
// MSGRAM_CPU1_TO_CM : > CPU1TOCMMSGRAM0, type=NOINIT
// READ_DATA_RAM : > CMTOCPU1MSGRAM0, type=NOINIT
.TI.ramfunc : {} LOAD = CMBANK0_SECTOR0 | CMBANK0_SECTOR1 | CMBANK0_SECTOR4,
RUN = SRAM,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
