TMS320F28388D: Output ESC SYNC0 signal through GPIO

Hi Ben,

The ESCSS_SYNC_IO_CONFIG register is 0x88 as same as default.

I have some question.

I call ESCSS_enableSync0GpioMuxConnection() to set this register.

1. If I connect ESC to CPU2, which CPU need call ESCSS_enableSync0GpioMuxConnection function?

2. This function only set SYNC0_GPIO_EN bit but no SYNC0_IOPAD_SEL.

    Do we need to modify this register?

    We can't find definition of IOPAD detail. (We use GPIO34 as ESC_SYNC0)

Thanks,

Joshua

Hi Ben,

Do you have any updates?

Thanks,

Joshua

I'm sorry, I will try to get back to you this week.

Hi Collier, 

Do you have any update for this case?

Hi,

Joshua CH Li said:

1. If I connect ESC to CPU2, which CPU need call ESCSS_enableSync0GpioMuxConnection function?

This should be CPU2.

Also, I just shared this offline, but we have just released a new example this week in C2000WARE 5.03 that shows how to use SYNC0 pin, with instructions for setup!  

Example is only for F28P65X, and it is called EEPROM EMU and DC demo. 

Best Regards,

Ben Collier

Hi Ben, 

Thank you for your help.

We enable SYNC0 on 28P65, but we have some problem.

The Default ET1100 SYNC0 pulse width is 10us, but 28P65 is 100ns.

100ns is too small for our application.

 How can I change this setting?

Thanks,

Joshua

Joshua,

I think this has to be changed by the EtherCAT master. If you check the ET1100 datasheet, you will see the registers that you need to write.

So you have successfully ran the example? You will be the first customer feedback that I have gotten. What do you think of the EEPROM emulation feature? Is it something that you will consider using in your design? 

Best Regards,

Ben Collier

Hi Ben,

SYNC0 pulse width is configured by IP Core setting when using EtherCAT IP Core.

Please refer to ET1100 datasheet section II, register 0x982 - 0x983.

If not default value(10us), I think TI should have way to let this configuration changed by user.

Could you help us to check?

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Actually, I don't run example successfully.

I only refer some code about SYNC0 configuration.

Could you share more detail about EEPROM emulation feature?

If we use 2048 byte EEPROM, 

how many flash size would be occupied by this feature in 28P65? 

Thanks,

Joshua

Joshua,

Joshua CH Li said:

Please refer to ET1100 datasheet section II, register 0x982 - 0x983.

If not default value(10us), I think TI should have way to let this configuration changed by user.

Could you help us to check?

I don't see anything in our MCU for configuring pulse width. Could you reach out to Beckhoff with this question? I don't see anything in their ET1100 datasheet for configuring pulse width since this register is read only.

Joshua CH Li said:

If we use 2048 byte EEPROM, 

how many flash size would be occupied by this feature in 28P65? 

Flash on this MCU is divided into 400 word (800 byte) sectors. You would have to allocate 3 sectors for 2048 bytes of EEPROM.

We are planning to release an app note on this feature in a few weeks.

Best Regards,

Ben Collier

Hi Ben,

As ET1100 datasheet 0x982 - 983  which I share before,

If use IP Core, the SYNC pulse width is is depended on configuration.

It means depend on chip vendor who integrate this IP Core.

If use other, the SYNC pulse width is configured by EEPROM word 2.

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I think you should ask TI design Team directly.

Thanks,

Joshua 

Joshua CH Li said:

I think you should ask TI design Team directly.

Ok, I will see if they have any input. 

Hi Ben,

Do you have any updates?

Thanks,

Joshua

Joshua,

I've had an ongoing correspondence, please allow me until tomorrow to summarize their comments.

Best Regards,

Ben Collier