TMS320F280049C: EPWM trip set through CMPSS

Hi Johnny,

Pleas allow another day for me to review this. Thank you!

Best Regards,

Allison

Hi Allison,

Looking forward to team's support.

Adding second question for truly what customer wants to implement.

Best regards,

Johnny

Hi Johnny,

1) You can configure the CMPSS and EPWM modules so that when the comparator output is at a specific state (either high or low - you can configure which state is used), this can be used to alter the EPWM signal. This can be done by using the Digital Compare submodule DCAH/L and DCBH/L signal paths. Please see the below snippet and review this section of the TRM for further details. Is this the use case the customer is targeting?

2) So are you saying the issue is that the trip is occurring each cycle that the condition is true? This can be fixed if the customer uses the comparator output to trigger a one shot trip instead of a cycle by cycle trip. Would this resolve the issue for the customer?

3) If the condition for the CBC trip is still active when the flag is cleared, the flags will be set again - please see the below snippet from the TRM Trip Zone chapter that describes this.

Best Regards,

Allison

Hi Allison,

Thanks for your input.

1). Yes, it is the use case which customer is configuring as that.

2). Let me explain more. Initially, I also suggest customer with one shot trip while  considering customer's practical design mentioned below, it might have a problem.

When comparator digital output is at a specific state (0/1), saying 1 to trigger one-shot trip with TZISR, then executing once TZISR, before leaving the TZISR, we will manually cleared the flag. So that, if the condition for the trip is still active (comparator digital output ), then it executes again the interrupt. At this comment, digital output may still output with 1 if the positive input always > negative input, then it will trigger again one-shot TZISR, the behavior such that may still seem as level trigger, not edge trigger.

What customer expects is executing once TZISR, when it leaves the ISR, how to know the next time when digital output changes from 0 to 1 as a edge trigger, then if that edge occurs, then trigger once again the TZISR. So that, it won't happen with CPMSS positive input always > negative input, then continue triggering one shot trip with TZISR. Hope the description is clear.

Thanks and regards,

Johnny

Hi Johnny,

Allison is currently out of office; please expect a delayed response. I apologize for any inconvenience.

Best Regards,

Delaney

Hi Johnny,

Thanks for the patience. So are you saying the customer needs the trip to occur only on comparator edges (for example, 0-->1 or 1-->0) instead of occurring based on the state of the comparator output? Has the customer considered using the ECAP? I can check with an ECAP expert on whether this could be a use case.

Best Regards,

Allison

Johnny Chen said:

What customer expects is executing once TZISR, when it leaves the ISR, how to know the next time when digital output changes from 0 to 1 as a edge trigger, then if that edge occurs, then trigger once again the TZISR.

Perhaps try to clear RS output latch (CMPSS) before exit the ISR handler. There is likely threshold CMPSS ± inputs electrical specification section. May clarify the edge conditions behavior and software can add hysteresis to CMPSS inputs too soften edges. Could also add comparator blanking ePWM configuration control when/how CMPSS will/can react to PWM period of generator A/B output duty cycle.

/* Set 3x hysteresis on comparator inputs */
CMPSS_setHysteresis(obj->cmpssHandle[cnt], 3);

// SW clear high comparator digital filter output latch
CMPSS_clearFilterLatchHigh(obj->cmpssHandle[cnt]);
/* Delay 10us */
DEVICE_DELAY_US(1);
// SW clear low comparator digital filter output latch
CMPSS_clearFilterLatchLow(obj->cmpssHandle[cnt]);

       /* Set the DC-1A/1B BLANKWDW to sync PWM periods
         * TRM: 18.1.4.2 PG.1878 Figures 18-54/55 */
        //EPWM_setDigitalCompareBlankingEvent(obj->pwmHandle[cnt], EPWM_DC_WINDOW_START_TBCTR_ZERO);
																//EPWM_DC_WINDOW_START_TBCTR_PERIOD

        /* Set DCx offset between window start pulse and blanking
         * window in number TBCLK's(10ns), offset=10µs  */
        //EPWM_setDigitalCompareWindowOffset(obj->pwmHandle[cnt], 1000);

        /* Set DCx filter blanking window width TBCLK(10ns), width=5µs */
        //EPWM_setDigitalCompareWindowLength(obj->pwmHandle[cnt], 500);

        /* Enable the DCx Blanking window */
        //EPWM_enableDigitalCompareBlankingWindow(obj->pwmHandle[cnt]);

        /* Sset the Edge filter mode for Rise/Fall */
        //EPWM_setDigitalCompareEdgeFilterMode(obj->pwmHandle[cnt], EPWM_DC_EDGEFILT_MODE_RISING);

        /* Set DC filter 1 edge count required to trigger DC events */
        //EPWM_setDigitalCompareEdgeFilterEdgeCount(obj->pwmHandle[cnt], EPWM_DC_EDGEFILT_EDGECNT_1);

        /* Enable the DC edge filter */
        //EPWM_enableDigitalCompareEdgeFilter(obj->pwmHandle[cnt]);

Hi Allison,

For the first time, the TZISR (1st) occurs based on the state of the comparator output. Then, following, the next TZISR (2nd) occurs again for the second time ONLY when comparator edge changes state from 0-->1.

That means the sequence will be in such:

1. CMPSS V+ > V-, then comparator outputs 1

2. Having the TZISR occur for the first time (1st TZISR occurs)

3. CMPSS V+ > V- continually so that the comparator output remains 1

4. Trigger the second time TZISR ONLY for comparator output edge trigger (so comparator output 1 (status in step 3) --> 0 -->1 (2nd TZISR occurs at the moment)), of course did clear the 1st TZISR flag in somewhere else before being able to trigger the 2nd TZISR.

For using ECAP, we can't know whether the CMPSS V+ > V- criteria also satisfices or not at the same time, to trigger the TZISR unless polling the comparator output in SW as well.

Thanks and regards,

Johnny

Hi Johny,

Directly from x49c TRM, a customer has to do some research to fully understand how the CMPSS works.

16.6 Using the CMPSS
16.6.1 LATCHCLR, EPWMSYNCPER and EPWMBLANK Signals
The LATCHCLR signal holds the digital filter, synchronization block and the latch output in reset (0) after the
required delays. It is activated in software using xLATCHCLR(x= “H” or “L”). It can also be activated by
EPWMSYNCPER when xSYNCCLREN(x= "H" or "L") is set. If a longer LATCHCLR signal is required, the
EPWMBLANK signal can be used to extend it by setting BLANKEN.
EPWMSYNCPER and EPWMBLANK (BLANKWDW) come from the Time-Base and Digital Compare
submodules of the EPWM, respectively. For a detailed description of how these two signals are generated, refer
to the respective submodule section in the Enhanced Pulse Width Modulator (ePWM) chapter.
The EPWMSYNCPER signal that loads DACxVALA when COMPDACCTL [SWLOADSEL] = 1 is a level trigger
load. If TBCTR and TBPRD of the EPWM are both 0, EPWMSYNCPER will be held at level high and DACxVALA
will be loaded immediately from DACxVALS irrespective of the value of COMPDACCTL [SWLOADSEL]. Due to
this, it is recommended to configure the EPWM first before setting COMPDACCTL [SWLOADSEL] to 1.
Note
The name of the sync signal that the CMPSS receives from the EPWM has been updated from
PWMSYNC to EPWMSYNCPER (SYNCPER/PWMSYNCPER/EPWMxSYNCPER) to avoid confusion
with the other EPWM sync signals EPWMSYNCI and EPWMSYNCO. For a description of what are
these signals, see the Enhanced Pulse Width Modulator (ePWM) chapter.
16.6.2 Synchronizer, Digital Filter and Latch Delays
The synchronization block adds a delay of 1-2 sysclks. If the digital filter is bypassed (all filter settings are 0), the
digital filter will add a delay of 2 sysclks. The latch adds 1 sysclk delay.
www.ti.com Comparator Subsystem (CMPSS)
SPRUI33D –

16.6.3 Calibrating the CMPSS
The CMPSS has two sources of offset errors: comparator offset error and compdac offset error. In the data
manual, the comparator offset error is referred to as Input referred offset error and compdac offset error is
referred to as Static offset error. See the device specific data manual for their values.
If both inputs of the comparator are driven from a pin, only the comparator offset error applies. However if the
inverting input of the comparator is driven from the compdac, then only the compdac offset error applies. This is
because the compdac offset error includes comparator offset error.
Due to the offset errors, it is recommended that the CMPSS be calibrated to ensure trips happen at the expected
levels. The flow below outlines how the calibration can be performed if the inverting input of the comparator is
driven from the compdac.
Notes before calibration:
1. A static DC signal is required on the non-inverting input of the comparator.
2. Hysteresis should be disabled for calibration. It can be re-enabled after calibration is complete.
3. A noisy input can make calibration difficult so it is recommended to use the latch with non-zero filter settings
depending on how noisy the signal on the non-inverting input is.
This approach sweeps down the compdac:
1. Set the starting compdac value to max, 0xFFF.
• Optional: Instead of setting the starting compdac value to max, it can be set to Vtarget + Static offset
error + Margin. Where Vtarget is the approximate DC voltage on the non-inverting input, Static offset
error is the compdac offset error specification and Margin is some amount of guard band. This can lead
to a faster calibration but will only work if Vtarget is known. Alternatively if Vtarget is unknown, the ADC
can be used to convert it.
2. Decrement compdac value by 1.
3. Wait for compdac to settle.
4. Clear latch.
5. Wait for possible latch set.
6. If latch is set, trip code is found exit.
• Optional: The trip code can be double checked by:
a. Increasing compdac value by 1.
b. Clear latch.
c. Wait for possible latch set.
d. Latch should be unset.
7. If latch is unset, go back to step 2 and repeat.
It is also possible to calibrate the CMPSS if both inputs of the comparator are driven from a pin. For this case,
the flow stays the same but the voltage on the inverting pin of the comparator is swept externally.
16.6.4 Enabling and Disabling the CMPSS Clock
If the clock to the CMPSS module is disabled while the comparator is active, the following behavior can be
expected:
• The comparator remains unaffected and will continue to trip from voltages on its inputs.
• If the reference 12-bit DAC is driving the negative input of the comparator, the voltage on the negative input
remains static and unaffected but DACVALA would no longer be updated from the ramp generator or
DACVALS.
• The ramp generator, synchronize block and digital filter freeze on their current states.
Enabling the clock to the CMPSS restores it to the state before the clock was disabled.

Hello,

The appropriate expert for this question is currently out of office, returning on Monday 9/16. Please expect a response back by then.

Thank you,

Luke

Hi Johny & Luke

In the meantime, consider:

Seemingly it is not advised to switch from one shot into continuous level detection flags during an ISR due to delay software setup times. Either set CMPSS and ePWM DACS for continuous ISR's that change ePWM duty cycle (reducing inverter power) until the CMPSS trip fault condition clears when inverter load is reduced or configure one-shot fault trip mode. Both are level trips (by design) that is how the comparator works, via DACVAL-L/H loaded values. Software can set a delay timer to clear a one-shot fault automatically or clear fault flag manually via Emergency push button input GPIO port. 

The accuracy of the level comparator relies on how well it is calibrated as mentioned above. There is always a small offset threshold between Pos & Neg comparator inputs, typically -20mV. Page 141-142 x49c datasheet.