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TMS320F28374S: watchdog reset

jane huang
Prodigy 90 points

Part Number: TMS320F28374S

Tool/software:

hi, expert:

we use WDCR=0 to reset , most of the time, GPIO will pulled down during reset, that is ok.

but some time, from AD stop to XRS changed, it last for 27ms, during that time, the GPIO is not set to 0 or pull up, it is changing.

in curcuit, GPIO is all pull down. 

my question, how to keep GPIO to 0 during reset.

ch1: XRS signal; ch2: GPIO in AD interrupt

  • 0
    TI__Mastermind 19876 points

    Hi Jane,

    If the watchdog is configured to reset the device, then the WDRST signal pulls the device reset (XRS) pin low for 512 INTOSC1 cycles when the watchdog counter reaches the maximum value.

    jane huang said:
    but some time, from AD stop to XRS changed, it last for 27ms, during that time, the GPIO is not set to 0 or pull up, it is changing.

    - Can you provide exact scenario I still don't understand your issue here ?
    What do you mean by AD stop to Xrsn change ? Can you show that in the scope snapshot ?

    jane huang said:
    my question, how to keep GPIO to 0 during reset.

    - This is driven by MCU as explained above.

    Thanks

  • 0 in reply to Prarthan Bhatt
    Prodigy 90 points

    hi, Prarthan:

    thanks for your help.

    we want to keep GPIO50 to low all the time even when the watchdog reset( set WDCR=0). 

    CPIOCTRLREG.GPBPUD.BIT.gpio50 =1 

    CPIOCTRLREG.GPBGMUX1.BIT.gpio50 =0

    CPIOCTRLREG.GPBMUX1.BIT.gpio50 =0

    CPIOCTRLREG.GPBDIR.BIT.gpio50 =0

    in curcuit, GPIO50 is pull down to ground.

    most of time, it works ok,GPIO50 keep to low when the watchdog reset.

    but some time, the GPIO50 is low first.  when running watchdog reset, it will chages in uncertainly state before XRS signal chage to low, the uncertainly state will last around 30ms.

    then, we set GPIO51 to pull-up disable and output state, it  toggles when goes into AD interrupt, it shows GPIO51 work nomal at first, but innormal for 27ms, during that time, GPIO50 is uncertainly state just as GPIO51. after 27ms, the XRS  signal chage to low.

    what makes that GPIO50 GPIO51 in uncertainty state?

    thanks

  • 0 in reply to jane huang
    TI__Mastermind 19876 points

    Is GPIO50 tied to Ground in PCB ? 
    Also GPIO is in input mode so its not driven by mcu so the gpio is only affected by the Ground its connected to.

    On watchdog reset, IO's go to Hi-Z state otherwise I cant think of anything affecting it.

    Thanks.