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TMDSCNCD280039C: C2000 microcontrollers forum

Part Number: TMDSCNCD280039C


Tool/software:

how to reset the NewDat bit in the CAN_IF3MCTL register?

if( CanaRegs.CAN_IF3MCTL.bit.NewDat )
{
rxA.all = CanaRegs.CAN_IF3DATA.all;
rxB.all = CanaRegs.CAN_IF3DATB.all;
HWREG_BP(myCANA_BASE +CAN_O_IF3OBS) = CAN_IF3OBS_MASK |CAN_IF3OBS_ARB |CAN_IF3OBS_CTRL|CAN_IF3OBS_DATA_A|CAN_IF3OBS_DATA_B;

// CanaRegs.CAN_IF3OBS.all =(bp_32)0x1F;

 Even though I read the CanaRegs.CAN_IF3DATA and CanaRegs.CAN_IF3DATB registers, the NewDat bit is not reset. I don't know what to do or how to reset it.

  • Hi Oleg,

    Writing 0x7F and message number to IFxCMD register will trigger the message transfer from message RAM to IF registers, and the bits NewDat and IntPnd are cleared.

  • Hi Wang.
    There is no IF3CMD register in the IF3 registers set. This is the problem.

  • Hi Oleg,

    The IF3x registers can automatically receive control and data from the Message RAM when a message object has been updated after reception of a CAN message. The CPU does not need to initiate the transfer from Message RAM to IF3 Register set.

    The NewDat and IntPnd should be cleared after the transfer has been completed.

  • Hi Van!
    You write: NewDat and IntPnd must be cleared after the transfer is complete.
    I don't understand what you mean after the transfer is complete. Does it happen after reading the IF3DATA registers or should something else be done.
    Could you write an example of how to read the data in a few lines of the program. Then all questions will be removed. Regards
    Oleg.

  • Hi Oleg,

    I will run a test, and come back to you later today.

  • Hi Oleg,

    The NewDat and IntPnd in MCTL register are not reset by reading the IF3x data registers (or mask, Arb registers). 

    The IF3OBS[4:0] are used to determine which data sections of the IF3 registers (ARB, MCTL, MSK, and DATA A, DATA B). If IF3OBS[4:0]=0x1F, the IF3x registers are updated automatically with new data only after the ARM/MCTL/MASK and data registers are read. If IF3OBS[4:0]=0x1A, the IF3x registers are updated with new data after data registers and ARB register are read. The interrupt is generated when IF3x registers are updated.

    I use the following code for IF3x registers configuration:

    // Enable DE3 bit in CTL register to trigger DMA when IF3 receives data
    canREG->CTL |= (1U << 20U);

    // Read DATA A & B, ARB, MASK, and CTL bits */
    canREG->IF3OBS = 0x1F; //0x1A;

    // Message box 2 configured for auto update
    canREG->IF3UEy[0]= 0x000002;

  • Hi QJ Wang!

    1. I don't use DMA.

    2. This is my test programme : 100

    CanaRegs.CAN_IF3UPD = BIT0;
    CanaRegs.CAN_IF3OBS.all = 0x1F; // read DATAA & DATAB
    CanaRegs.CAN_CTL.bit.DE3 = 1;


    if3: while (CanaRegs.CAN_IF3MCTL.bit.NewDat)
    {
    canaShadow = CanaRegs;
    dbg_rxA = CanaRegs.CAN_IF3DATA.all;
    dbg_rxB = CanaRegs.CAN_IF3DATB.all;

    dbg_if3++;
    DEVICE_DELAY_US(1000u * 10u); // задержка на миллисекунды
    }
    goto if3;

    3. I send message to mailbox BIT0 every second

    4. The bit (CanaRegs.CAN_IF3MCTL.bit.NewDat) never reset .

    I don't know what I have to do.

    Now I solved this problem via IF2 registers set. 

  • CanaRegs.CAN_IF3OBS.all = 0x1F; // read DATAA & DATAB

    To reset NewDat, you have to read ARB, MCTL, MASK, dataA and dataB registers