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TMS320F28P650DK: Max CLB clock when SYSCLK = EPWMCLK = 200 MHz

Wayne Huang
Genius 17195 points

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi Champs,

I am asking this for our customer.

When the user uses SYSCLK = EPWMCLK = 200 MHz, does that mean CLB clock can be 100 MHz at maximum because CLB clock cannot exceed 150 MHz in 8.2.1 CLB Clock of TRM ?

(Note that SYSCLK = EPWMCLK = 200 MHz is a hard requirement here.)

Q1:

We uses Sysconfig Clocktree below. 

Would you please confirm the configuration below is correct?

Q2: 

In TRM Table 3-194 below for CLBCLKCTL, the bits are reserved. The user does not see CLBCLKDIV, TILECLKDIV.

Is there anything wrong?

By using Sysconfig clocktree above, can CLB clock be set correctly?

  • 0
    TI__Mastermind 28580 points

    Hi Wayne,

    From looking at the spec the TILECLKDIV and CLBCLKDIV bits still exist but are hidden from the customer as of now. The clocktree tool should be able to configure these bits.

    I will verify with design why these bits are hidden.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    TI__Genius 17195 points

    Hi Luke,

    Please also confirm the clocktree tool can "correctly" set TILECLKDIV and CLBCLKDIV bits for CLB clock at 100 MHz.

    By default, clocktree tool does not set 100MHz like I showed above, so I am not sure if there is any concern.

    It makes more sense to use 200 MHz SYSCLK/EPWMCLK and 100 MHz CLB by default on F28P65x device.

    Besides, F2838x TRM does show TILECLKDIV and CLBCLKDIV bits.

    The user is migrating their codes from F2838x onto F28P65x and found this issue, but the user did not use clocktree tool on F2838x.

    SysCtl_setCLBClk is available in F2838x driverlib/sysctl.h, but it's not available in F28P65x counterpart, and this is why we are confused if and how F28P65x clocktree can set CLB clock.

    Therefore, please confirm all these (F28P65x clocktree tool/TRM) and let us know how to do next.

  • 0 in reply to Wayne Huang
    TI__Mastermind 28580 points

    Hi Wayne,

    I've tested modifying the CLBCLKCTL bits that were marked as design but it doesn't seem to change the CLB clock frequency. It's possible these clock dividers are hard coded with some value and the values programmed in the register are ignored. I'm getting confirmation from the design team on this.

    If these bits are hardcoded in design then the clocktree tool will have no impact on the CLB clock frequency. Modifying the CLB clock dividers in the clocktree GUI does not have any impact on the generated code either.

    I'll respond back to you when I get more information from the design team.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    TI__Mastermind 28580 points

    Hi Wayne,

    After further testing I realized that the CLB clock dividers only take effect if the "asynchronous" clock is selected in the CLBCLKCTL register. After doing this I am able to see the effect of the clock dividers.

    Still, it seems there's an issue with the clock tree tool in that it's not modifying the CLBCLKCTL dividers when modifying the GUI. There are also missing driverlib functions to configure these bits.

    I will make sure driverlib and sysconfig are corrected to include these, for now the customer will need to manually modify the value of CLBCLKCTL according to the following register description:

    Register Name CLBCLKCTL
    Field Range Design Name Description HW Reset Value R/W Reset Type Detailed Description
    2..0 CLBCLKDIV CLB clock divider configuration. 0x7 R/W SYSRSn 000: /1
    001: /2
    010: /3
    011: /4
    100: /5
    101: /6
    110: /7
    111: /8
    3 Reserved Reserved 0 R=0 SYSRSn Reserved
    4 TILECLKDIV CLB Tile clock divider configuration. 0 R/W SYSRSn 0: /1
    1: /2
    15..5 Reserved Reserved 0 R=0 SYSRSn Reserved
    16 CLKMODECLB1 Clock mode of CLB1 0 R/W SYSRSn 0 : CLB1 is synchronous to SYSCLK
    1 : CLB1 runs of asynchronous clock
    17 CLKMODECLB2 Clock mode of CLB2 0 R/W SYSRSn 0 : CLB2 is synchronous to SYSCLK
    1 : CLB2 runs of asynchronous clock
    18 CLKMODECLB3 Clock mode of CLB3 0 R/W SYSRSn 0 : CLB3 is synchronous to SYSCLK
    1 : CLB3 runs of asynchronous clock
    19 CLKMODECLB4 Clock mode of CLB4 0 R/W SYSRSn 0 : CLB4 is synchronous to SYSCLK
    1 : CLB4 runs of asynchronous clock
    20 CLKMODECLB5 Clock mode of CLB5 0 R/W SYSRSn 0 : CLB5 is synchronous to SYSCLK
    1 : CLB5 runs of asynchronous clock
    21 CLKMODECLB6 Clock mode of CLB6 0 R/W SYSRSn 0 : CLB6 is synchronous to SYSCLK
    1 : CLB6 runs of asynchronous clock
    31..24 Reserved Reserved 0 R=0 SYSRSn Reserved
  • 0 in reply to Luke Jones
    TI__Genius 17195 points

    Hi Luke,

    What about SYNC mode?

    Does SYNC here means CLB clock is synchronous with SYSCLK and EPWMCLK? 

    If the user wants to get signals from an EPWM and then output to the EPWM, does it mean SYNC mode is required?

    Why these two bits cannot be used in SYNC mode?

    In SYNC mode, what frequency is the CLB clock running at here when SYSCLK=EPWMCLK=200MHz?

  • 0 in reply to Wayne Huang
    TI__Mastermind 28580 points

    Hi Wayne,

    Based on my testing, the CLB clock will be equal to either SYSCLK or EPWMCLK. Changing the CLB clock dividers had no effect on the CLB clock frequency. I will confirm later this week which clock the CLB clock matches when in synchronous mode.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    TI__Genius 17195 points

    Hi Luke,

    Do you have any update?

  • 0 in reply to Wayne Huang
    TI__Genius 17195 points

    Hi Luke,

    1.

    Can you confirm that in SYNC mode, what frequency is the CLB clock running at here when SYSCLK=EPWMCLK=200MHz?

    Is CLB clock running at 100 MHz by default?

    2.

    In SYNC mode, there can be 1 or 2 cycle CLB delay for CLB to latch the signals from outside. Is my understanding correct?

    3. In ASYNC mode, the user can modify the CLBCLKCTL register you showed above to configure CLB clock at 100 MHz, and F28P65x TRM will be updated later. Is it correct?

  • 0 in reply to Wayne Huang
    TI__Mastermind 28580 points

    Hi Wayne,

    Apologies for the delayed response. I have tested this on my side and confirmed the following.

    1. In SYNC mode, CLB clock is always equal to EPWMCLK. I tested this by using the CLB prescaled clock as an input to the CLB and routed to a GPIO using CLB output XBAR. Since EPWMCLKDIV is 01 by default, the CLB clock will be 100 Mhz by default

    2. There is only a delay when input synchronization is used on an input to the CLB. This is recommended on some inputs but not all. The inputs that require synchronization are specified in the CLB input tables in the CLB chapter as well as through warning messages in sysconfig.

    3. This is correct.

    Let me know if you have further questions.

    Thank you,

    Luke