Other Parts Discussed in Thread: C2000WARE
Tool/software:
Good morning,
I'd like to calculate the CRC of our application from the linker. I read the Linker-Generated CRC Tables section in the guide and seems feasible for us.
The sections I'd like to calculate the CRC from are the FLASH1 | FLASH2 | FLASH3 | FLASH4 | FLASH5 | FLASH6 | FLASH7 | FLASH8 | FLASH9.
I wrote this code:
CLA_SCRATCHPAD_SIZE = 0x100;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
MEMORY
{
/* BEGIN is used for the "boot to Flash" bootloader mode */
BEGIN : origin = 0x080000, length = 0x000002
BOOT_RSVD : origin = 0x000002, length = 0x0001AE /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B0, length = 0x000250
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
/* RAMD0 : origin = 0x00C000, length = 0x000800 */
/* RAMD1 : origin = 0x00C800, length = 0x000800 */
RAMD01 : origin = 0x00C000, length = 0x001000
/* RAMLS0_to_LS7 : origin = 0x008000, length = 0x004000 */
RAMLS0_to_LS3 : origin = 0x008000, length = 0x002000
/* RAMLS0 : origin = 0x008000, length = 0x000800 */
/* RAMLS1 : origin = 0x008800, length = 0x000800 */
/* RAMLS2 : origin = 0x009000, length = 0x000800 */
/* RAMLS3 : origin = 0x009800, length = 0x000800 */
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5_to_LS6 : origin = 0x00A800, length = 0x001000
// RAMLS5 : origin = 0x00A800, length = 0x000800
// RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMGS0_to_7 : origin = 0x00D00C, length = 0x007FF4
/* RAMGS0 : origin = 0x00D000, length = 0x001000
RAMGS1 : origin = 0x00E000, length = 0x001000
RAMGS2 : origin = 0x00F000, length = 0x001000
RAMGS3 : origin = 0x010000, length = 0x001000
RAMGS4 : origin = 0x011000, length = 0x001000
RAMGS5 : origin = 0x012000, length = 0x001000
RAMGS6 : origin = 0x013000, length = 0x001000
RAMGS7 : origin = 0x014000, length = 0x001000 */
RAMGS8 : origin = 0x015000, length = 0x001000
RAMGS9 : origin = 0x016000, length = 0x001000
RAMGS10 : origin = 0x017000, length = 0x001000
RAMGS11 : origin = 0x018000, length = 0x001000
RAMGS12 : origin = 0x019000, length = 0x001000
RAMGS13 : origin = 0x01A000, length = 0x001000
RAMGS14 : origin = 0x01B000, length = 0x001000
RAMGS15 : origin = 0x01C000, length = 0x001000
/* Flash sectors */
FLASH0 : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASH1 : origin = 0x082000, length = 0x002000 /* on-chip Flash */
FLASH2 : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASH3 : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASH4 : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASH5 : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASH6 : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASH7 : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASH8 : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASH9 : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASH10 : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASH11 : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASH12 : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASH13 : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */
/*-------------*/
/* CPU1 to CPU2*/
/*-------------*/
/* Ram space for ADC-D converted values.
IT MUST BE THE SAME IN SLAVE LINKER FILE and coherent to what specified in AdcDriver.h!!!
Length 0x06 means: (3 channels -> conversion -> 3 FLOAT32 = 6 word
As consequence, CPU1TOCPU2RAM will start 6 words after its natural beginning.
*/
ADCD_VALUES_RAM : origin = 0x03A000, length = 0x000006
/* CPUxTOCPUy_SERV is a shared memory to exhange services between CPUs. */
CPU1TOCPU2_SERV : origin = 0x03A006, length = 0x0000F0
/* CPU1 Serial Flash Lock */
CPU1TOCPU2_SFLOCK : origin = 0x03A0F6, length = 0x000002
/* CPU1 Fault IGBT status for axis 2*/
CPU1TOCPU2_FAULTIGBT : origin = 0x03A0F8, length = 0x000002
/* IPC. IT MUST BE GREATER THEN 144 WORDS (SEE IPC_CPU1_To_CPU2_PutBuffer ipc.c)*/
CPU1TOCPU2RAM : origin = 0x03A0FA, length = 0x000706
/*-------------*/
/* CPU2 to CPU1*/
/*-------------*/
/* Diagnostic data from CPU2 to CPU1*/
CPU2TOCPU1RAM_DIA : origin = 0x03B000, length = 0x000020
/* CPUxTOCPUy_SERV is a shared memory to exhange services between CPUs. */
CPU2TOCPU1_SERV : origin = 0x03B020, length = 0x0000F0
/* Axis 2 State */
CPU2TOCPU1_AXSTATE : origin = 0x03B110, length = 0x000002
/* CPU2 Serial Flash Lock */
CPU2TOCPU1_SFLOCK : origin = 0x03B112, length = 0x000002
/* IPC. IT MUST BE GREATER THEN 144 WORDS (SEE IPC_CPU1_To_CPU2_GetBuffer ipc.c)*/
CPU2TOCPU1RAM : origin = 0x03B114, length = 0x0006EC
/*----------------*/
/* CM to/from CPUx*/
/*----------------*/
CMTOCPURAM0_IPC : origin = 0x038000, length = 0x000200 /* IPC. IT MUST BE GREATER THEN 144 WORDS (SEE IPC_CPU_To_CM_GetBuffer ipc.c)*/
CMTOCPURAM0_PDO : origin = 0x038200, length = 0x000040 /* PDO CM to CPU1 */
CMTOCPURAM0_FSOE_STD : origin = 0x038240, length = 0x000038 /* FSoE Standard Chn to CPU1 - 0x38 must be graeter than MAX_FSOE_STD_SIZE+2 */
CMTOCPURAM0_FSOE_FST : origin = 0x038278, length = 0x000008 /* FSoE Fast Chn to CPU1 - 0x08 must be graeter than MAX_FSOE_FST_SIZE+2 */
CMTOCPURAM0_SERV : origin = 0x038280, length = 0x000060 /* SERV CM to CPU1 - 60 is just random */
CMTOCPURAM0_ECTST : origin = 0x0382E0, length = 0x000002 /* Ecat state from CM */
CMTOCPURAM0 : origin = 0x0382E2, length = 0x00011E /* free */
CMTOCPURAM1 : origin = 0x038400, length = 0x000400 /* free */
CPUTOCMRAM0_IPC : origin = 0x039000, length = 0x000200 /* IPC. IT MUST BE GREATER THEN 144 WORDS (SEE IPC_CPU_To_CM_PutBuffer ipc.c)*/
CPUTOCMRAM0_PDO : origin = 0x039200, length = 0x000040 /* PDO CPU1 to CM */
CPUTOCMRAM0_FSOE_STD : origin = 0x039240, length = 0x000038 /* FSoE Standard Chn from CPU1 - 0x38 must be graeter than MAX_FSOE_STD_SIZE+2 */
CPUTOCMRAM0_FSOE_FST : origin = 0x039278, length = 0x000008 /* FSoE Fast Chn from CPU1 - 0x08 must be graeter than MAX_FSOE_FST_SIZE+2 */
CPUTOCMRAM0_SERV : origin = 0x039280, length = 0x000060 /* SERV CPU1 to CM - 60 is just random */
CPUTOCMRAM0 : origin = 0x0392E0, length = 0x000120 /* free */
CPUTOCMRAM1 : origin = 0x039400, length = 0x000400 /* free */
/*-------------------*/
/* Global Shared RAM - Beginning of RAMGS0*/
/*-------------------*/
BBHENDATPOSITIONS : origin = 0x00D000, length = 0x00000C
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
CLA1_DMA_MSGRAM : origin = 0x001680, length = 0x000080
DMA_CLA1_MSGRAM : origin = 0x001700, length = 0x000080
}
SECTIONS
{
codestart : > BEGIN, ALIGN(4)
.text : >> FLASH1 | FLASH2 | FLASH3 | FLASH4 | FLASH5 | FLASH6 | FLASH7 | FLASH8 | FLASH9, ALIGN(4)
.cinit : > FLASH1 | FLASH2 | FLASH3 | FLASH4 | FLASH5 | FLASH6 | FLASH7 | FLASH8 | FLASH9, ALIGN(4)
.switch : > FLASH1, ALIGN(4)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM1
#if defined(__TI_EABI__)
.init_array : > FLASH1, ALIGN(4)
.bss : >> RAMLS0_to_LS3 | RAMLS4
.bss:output : >> RAMLS4
.bss:cio : >> RAMLS4
.data : >> RAMLS0_to_LS3 | RAMLS4
.sysmem : >> RAMLS4
/* Initalized sections go in Flash */
.const : > FLASH5, ALIGN(4)
#else
.pinit : > FLASH1, ALIGN(4)
.ebss : >> RAMLS4
.esysmem : >> RAMLS4
.cio : >> RAMLS4
/* Initalized sections go in Flash */
.econst : >> FLASH4 | FLASH5, ALIGN(4)
#endif
ramgs0 : > RAMGS0_to_7, type=NOINIT
ramgs3 : > RAMGS0_to_7, type=NOINIT
ADCD_VALUES_CPU2 : > ADCD_VALUES_RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1_DIA : > CPU2TOCPU1RAM_DIA, type=NOINIT /* 8+1 words of diagnostic data from CPU2 to CPU1*/
MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, type=NOINIT
MSGRAM_CPU_TO_CM : > CPUTOCMRAM0_IPC, type=NOINIT
MSGRAM_CM_TO_CPU : > CMTOCPURAM0_IPC, type=NOINIT
CM_TO_CPU_SERV : > CMTOCPURAM0_SERV, type=NOINIT
CM_TO_CPU_PDO : > CMTOCPURAM0_PDO, type=NOINIT
CM_TO_CPU_FSOE_STD : > CMTOCPURAM0_FSOE_STD, type=NOINIT
CM_TO_CPU_FSOE_FST : > CMTOCPURAM0_FSOE_FST, type=NOINIT
CM_TO_CPU_ECTST : > CMTOCPURAM0_ECTST, type=NOINIT
CPU_TO_CM_SERV : > CPUTOCMRAM0_SERV, type=NOINIT
CPU_TO_CM_PDO : > CPUTOCMRAM0_PDO, type=NOINIT
CPU_TO_CM_FSOE_STD : > CPUTOCMRAM0_FSOE_STD, type=NOINIT
CPU_TO_CM_FSOE_FST : > CPUTOCMRAM0_FSOE_FST, type=NOINIT
CPU1_TO_CPU2_SERV : > CPU1TOCPU2_SERV, type=NOINIT
CPU1_TO_CPU2_SFLOCK : > CPU1TOCPU2_SFLOCK, type=NOINIT
CPU2_TO_CPU1_SERV : > CPU2TOCPU1_SERV, type=NOINIT
CPU2_TO_CPU1_SFLOCK : > CPU2TOCPU1_SFLOCK, type=NOINIT
CPU2_TO_CPU1_AXSTATE : > CPU2TOCPU1_AXSTATE, type=NOINIT
CPU1_TO_CPU2_FAULT_IGBT : > CPU1TOCPU2_FAULTIGBT, type=NOINIT
BBH_ENDAT_POSITIONS : > BBHENDATPOSITIONS, type=NOINIT
/* The following section definition are for SDFM examples */
// Filter_RegsFile : > RAMGS0
// Filter1_RegsFile : > RAMGS1, fill=0x1111
// Filter2_RegsFile : > RAMGS2, fill=0x2222
// Filter3_RegsFile : > RAMGS3, fill=0x3333
// Filter4_RegsFile : > RAMGS4, fill=0x4444
// Difference_RegsFile : >RAMGS5, fill=0x3333
/* CLA specific sections *////////////////////////////////////////////
#if defined(__TI_EABI__)
Cla1Prog : LOAD = FLASH9,
RUN = RAMLS5_to_LS6,
LOAD_START(Cla1funcsLoadStart),
LOAD_END(Cla1funcsLoadEnd),
RUN_START(Cla1funcsRunStart),
LOAD_SIZE(Cla1funcsLoadSize),
ALIGN(8)
#else
Cla1Prog : LOAD = FLASH9,
RUN = RAMLS5_to_LS6,
LOAD_START(_Cla1funcsLoadStart),
LOAD_END(_Cla1funcsLoadEnd),
RUN_START(_Cla1funcsRunStart),
LOAD_SIZE(_Cla1funcsLoadSize),
ALIGN(8)
#endif
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, type=NOINIT
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, type=NOINIT
Cla1ToDmaMsgRAM : > CLA1_DMA_MSGRAM, type=NOINIT
DmaToCla1MsgRAM : > DMA_CLA1_MSGRAM, type=NOINIT
Cla1DataRam : > RAMLS7
/* CLA C compiler sections */
//
// Must be allocated to memory the CLA has write access to
//
CLAscratch :
{ *.obj(CLAscratch)
. += CLA_SCRATCHPAD_SIZE;
*.obj(CLAscratch_end) } > RAMLS7
.scratchpad : > RAMLS7
.bss_cla : > RAMLS7
cla_shared : > RAMLS7
#if defined(__TI_EABI__)
.const_cla : LOAD = FLASH8,
RUN = RAMLS7,
RUN_START(Cla1ConstRunStart),
LOAD_START(Cla1ConstLoadStart),
LOAD_SIZE(Cla1ConstLoadSize)
#else
.const_cla : LOAD = FLASH8,
RUN = RAMLS7,
RUN_START(_Cla1ConstRunStart),
LOAD_START(_Cla1ConstLoadStart),
LOAD_SIZE(_Cla1ConstLoadSize)
#endif
/////////////////////////////////////////////////////////////////////////////
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASH3 | FLASH4,
RUN = RAMGS0_to_7
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(4)
#else
.TI.ramfunc : {} LOAD = FLASH3 | FLASH4,
RUN = RAMLS0_to_LS3,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
ALIGN(4)
#endif
/** Section for operation modes **/
UNION : run > RAMLS0_to_LS3
{
opm1funcs : LOAD > FLASH1,
LOAD_START(opm1funcsLoadStart),
LOAD_END(opm1funcsLoadEnd),
RUN_START(opm1funcsRunStart)
opm2funcs : LOAD > FLASH1,
LOAD_START(opm2funcsLoadStart),
LOAD_END(opm2funcsLoadEnd),
RUN_START(opm2funcsRunStart)
opm3funcs : LOAD > FLASH1,
LOAD_START(opm3funcsLoadStart),
LOAD_END(opm3funcsLoadEnd),
RUN_START(opm3funcsRunStart)
opm4funcs : LOAD > FLASH1,
LOAD_START(opm4funcsLoadStart),
LOAD_END(opm4funcsLoadEnd),
RUN_START(opm4funcsRunStart)
opm5funcs : LOAD > FLASH1,
LOAD_START(opm5funcsLoadStart),
LOAD_END(opm5funcsLoadEnd),
RUN_START(opm5funcsRunStart)
opm6funcs : LOAD > FLASH1,
LOAD_START(opm6funcsLoadStart),
LOAD_END(opm6funcsLoadEnd),
RUN_START(opm6funcsRunStart)
opm7funcs : LOAD > FLASH1,
LOAD_START(opm7funcsLoadStart),
LOAD_END(opm7funcsLoadEnd),
RUN_START(opm7funcsRunStart)
opm8funcs : LOAD > FLASH1,
LOAD_START(opm8funcsLoadStart),
LOAD_END(opm8funcsLoadEnd),
RUN_START(opm8funcsRunStart)
opm9funcs : LOAD > FLASH1,
LOAD_START(opm9funcsLoadStart),
LOAD_END(opm9funcsLoadEnd),
RUN_START(opm9funcsRunStart)
opm10funcs : LOAD > FLASH1,
LOAD_START(opm10funcsLoadStart),
LOAD_END(opm10funcsLoadEnd),
RUN_START(opm10funcsRunStart)
opm11funcs : LOAD > FLASH1,
LOAD_START(opm11funcsLoadStart),
LOAD_END(opm11funcsLoadEnd),
RUN_START(opm11funcsRunStart)
opm12funcs : LOAD > FLASH1,
LOAD_START(opm12funcsLoadStart),
LOAD_END(opm12funcsLoadEnd),
RUN_START(opm12funcsRunStart)
}
/** Section for update position function **/
UNION : run > RAMD01
{
updateValuesfuncs1 : LOAD > FLASH1
LOAD_START(updateValuesfuncs1LoadStart),
LOAD_END(updateValuesfuncs1LoadEnd),
RUN_START(updateValuesfuncs1RunStart)
updateValuesfuncs2 : LOAD > FLASH1
LOAD_START(updateValuesfuncs2LoadStart),
LOAD_END(updateValuesfuncs2LoadEnd),
RUN_START(updateValuesfuncs2RunStart)
}
UNION : run > RAMGS0_to_7
{
controller1_funcs : LOAD > FLASH1
LOAD_START(controller1_funcsLoadStart),
LOAD_END(controller1_funcsLoadEnd),
RUN_START(controller1_funcsRunStart)
controller2_funcs : LOAD > FLASH1
LOAD_START(controller2_funcsLoadStart),
LOAD_END(controller2_funcsLoadEnd),
RUN_START(controller2_funcsRunStart)
controller3_funcs : LOAD > FLASH1
LOAD_START(controller3_funcsLoadStart),
LOAD_END(controller3_funcsLoadEnd),
RUN_START(controller3_funcsRunStart)
controller4_funcs : LOAD > FLASH1
LOAD_START(controller4_funcsLoadStart),
LOAD_END(controller4_funcsLoadEnd),
RUN_START(controller4_funcsRunStart)
controller5_funcs : LOAD > FLASH1
LOAD_START(controller5_funcsLoadStart),
LOAD_END(controller5_funcsLoadEnd),
RUN_START(controller5_funcsRunStart)
controller6_funcs : LOAD > FLASH1
LOAD_START(controller6_funcsLoadStart),
LOAD_END(controller6_funcsLoadEnd),
RUN_START(controller6_funcsRunStart)
no_controller_funcs : LOAD > FLASH1
LOAD_START(no_controller_funcsLoadStart),
LOAD_END(no_controller_funcsLoadEnd),
RUN_START(no_controller_funcsRunStart)
}
/* Allocate IQ math areas: */
IQmath : > FLASH6, PAGE = 0, ALIGN(8) /* Math Code */
IQmathTables : > FLASH7, PAGE = 0, ALIGN(8)
UNION : run > RAMD01
{
Sf_cache_ram :
FLASH28_API : LOAD > FLASH3 | FLASH4
{
-l F2838x_C28x_FlashAPI.lib
}
LOAD_START(Flash28_API_LoadStart),
LOAD_END(Flash28_API_LoadEnd),
RUN_START(Flash28_API_RunStart),
ALIGN(4)
}
.codestart: {} crc_table(_my_crc_table_for_a1)
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
He gives me this warning:
#10199-D CRC table operator (_my_crc_table_for_a1) ignored for ".codestart": CRC table operator cannot be associated with empty output section 2838x_FLASH_lnk_ecat_cpu1.cmd /EvalBoard_CPU1-2 line 430 C/C++ Problem
How can I fix that? I have some problems in how I should fix this.
Thank you!
Luca Predieri
