Tool/software:
Situation example:
The CMPSS's compared voltage is set as 1.5V from internal DAC / external signal, once the sensed voltage on positive pin is higher than negative pin 1.5V, then trigger ONCE interrupt. Then, if the sensed voltage on positive pin keeps higher than 1.5V, then not triggering the interrupt again. Going on, An interrupt can only be triggered again until the sensed voltage on CMPSS positive input pin is first lower than 1.5V, and then come after higher 1.5V again, as a real edge trigger source for TZISR.
In simple terms, an interrupt occurs every time when the comparator output changes from 0 to 1. Is there a feasible workaround with CMPSS + EPWM module ? Currently multiple interrupts are being generated since CMPSS+EPWM's DCA/BEVT1/2 is level triggered.
