TMS320F28379D: BURST mode PWM at light loads for PSFB converter (i.e Turning On and OFF PWM)

Part Number: TMS320F28379D

Tool/software:

Hello,

I am generating a PWM for Phase shift PWM converter. I have a question regarding turning ON/OFF of PWM (turning OFF anf Turning ON) at very light loads or no-load condition.

So, the ADC sampling and acquisition happens at TBCTR=TBPRD and an ISR is called as soon as the last ADC channel acquisition is finished. The CMPA value however is updated at TBCTR=0.

 In order to replicate the burst mode, I have created a variable Vdc_pu1. If Vdc_pu1>410, I would like to turn off the pwm and if Vdc_pu1<390, I would like to turn on the PWM. But I want to do this as a known point of TBCTR =0. In order to do that, I started with the AQCSRFC register. Inside ISR I have the below code

     if(Vdc_pu1 > 410)

     {

//         FlagEnable.System1 = 0;

         GpioDataRegs.GPASET.bit.GPIO2=1;

 

         EPwm4Regs.AQSFRC.bit.RLDCSF = 00;

         EPwm4Regs.AQCSFRC.bit.CSFA = 01;

         EPwm4Regs.AQCSFRC.bit.CSFB = 01;
     }

I would like to turn off the EPQM4A, EPWM4B at TBCTR(EPWM4) = 0 and EPWM5A, EPWM5B at TBCTR(EPWM5) = 0. But for now I am not turning off the EPWM 5A and 5B. In the below picture EPWM 4A and EPWM 5A are in phase with each other (but in actual PSFB operation they may not be in phase, but for now in a simple case, I wanted to turn off EPWM 4A and 4B at TBCTR(EPWM4) = 0). When I use the above code I get the below results as shown in the picture. 

Channel1 - YELLOW - EPWM4A

Channel2 - BLUE - EPWM4B

Channel3 - RED - EPWM5A

Channel4 - GREEN - EPWM5B

Channel5 - Orange - GPIO (it is set when Vdc_pu1 >410)

When AQCSRFC is used for EPWM 4, 4A goes to zero but 4B goes high that is because 4A and 4B are configured to be complimentary to each other with a dead band of 400ns (a dead band module is used).

I tried to modify the code as below

     if(Vdc_pu1 > 410)

     {

//         FlagEnable.System1 = 0;

         GpioDataRegs.GPASET.bit.GPIO2=1;

 

         EPwm4Regs.AQSFRC.bit.RLDCSF = 00;

         EPwm4Regs.AQCSFRC.bit.CSFA = 01;

         EPwm4Regs.AQCSFRC.bit.CSFB = 01;

  EPwm4Regs.DBCTL.bit.POLSEL = 00;

         EPwm4Regs.AQCTLA.bit.ZRO = 01;

   EPwm4Regs.AQCTLB.bit.ZRO = 01;

}

But this give the below results. EPWM4A and EPWM4B are ON for some period and then they turn off.

Channel1 - YELLOW - EPWM4A

Channel2 - BLUE - EPWM4B

Channel3 - RED - EPWM5A

Channel4 - GREEN - EPWM5B

Channel5 - Orange - GPIO (it is set when Vdc_pu1 >410)

So, I would like to know if there is any way to shut down the PWM at a known point of TBCTR=0. Well, the ideal way I would like is to let the PWM finish their ON time, whatever it was, and then TURN OFF after their own period and not turn off for the next period.

I am also attaching the overall code. Please do let me know how can I proceed ahead. I don’t know if using TZFRC of trip zone will help me in turning off the PWM at a known period (as it happens instantaneously).

PSFB_w_MPPT2.rar

  • Hello,

    I understand you want to turn off the PWMs at a particular time in the PWM cycle (after they have completed their "on" time), but are also using the deadband module to generate complementary outputs, changing the action qualifiers to "do nothing" would result in a low channel A and high channel B (if I'm understanding your setup correctly). There are a few similar posts with this question of methods for shutting off EPWMs and ideas for implementation. Please let me know if you find them helpful first:

    Best Regards,

    Allison

  • "I understand you want to turn off the PWMs at a particular time in the PWM cycle (after they have completed their "on" time), but are also using the deadband module to generate complementary outputs, changing the action qualifiers to "do nothing" would result in a low channel A and high channel B (if I'm understanding your setup correctly)".

    Yes, It is correct. But the links that are shared suggest that there is no way to make the EPWM4A and EPWM4B to LOW using the AQCSRFC register if EPWM4A and EPWM4B are configured in a complementary fashion using the Dead-band module. But if I use Trip-zone, that will turn off the EPWM's instantly (and not at TBCTR(EPWM4) = 0).

    Do you have any suggestions to turn off (make them low) the EPWM4A and EPWM4B at TBCTR(EPWM4) = 0 and turn off EPWM5A and EPWM5B at TBCTR(EPWM5) = 0?

    I was almost able to get it turn off as I wanted. I.e I want to TURN OFF at after their own ON TIME is over as shown below in the picture 

    Channel1 - YELLOW - EPWM4A

    Channel2 - BLUE - EPWM4B

    Channel3 - RED - EPWM5A

    Channel4 - GREEN - EPWM5B

    Channel5 - Orange - GPIO (it is set when Vdc_pu1 >410)

    But there is a small kink in the EPWM4A and EPWM4B as shown in the above picture (after they finish their own period. I used a below code to achieve this. I am unable to figure out, how to get rid of that kink (where it appears that both EPWM4A and EPWM4B are trying to turn ON).

    if(Vdc_pu1 > 410)

         {

             GpioDataRegs.GPASET.bit.GPIO2=1;

     

             EPwm4Regs.AQSFRC.bit.RLDCSF = 00;

             EPwm4Regs.AQCSFRC.bit.CSFA = 01;

             EPwm4Regs.AQCSFRC.bit.CSFB = 01;

             EPwm4Regs.DBCTL2.bit.SHDWDBCTLMODE = 01;

             EPwm4Regs.DBCTL2.bit.LOADDBCTLMODE = 00;

             EPwm4Regs.DBCTL.bit.POLSEL = 00;

             EPwm4Regs.DBRED.bit.DBRED = 1000;

             EPwm4Regs.DBFED.bit.DBFED = 1000;

             EPwm4Regs.AQCTL.bit.SHDWAQBMODE = 01;

             EPwm4Regs.AQCTL.bit.SHDWAQAMODE = 01;

             EPwm4Regs.AQCTL.bit.LDAQAMODE = 00;

             EPwm4Regs.AQCTL.bit.LDAQBMODE = 00;

             EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;           

             EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;       

             EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;      

             EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR;

         }

    EPWM4A and EPWM5A are in phase with each other (for the experiment done in the above picture), and EPWM4B and EPWM5B are complimentary signals to EPWM4A and EPWM5A, respectively. So, as can be seen in the picture EPWM4B and EPWM5B, the EPWM4B is finishing its own cycle and then turning OFF but at TBCTR(EPWM4) = 0, both EPWM4A and EPWM4B are trying to turn On, producing a kink. 

    Do you have any suggestions to get rid of this kink? or is there any other to implement what I am trying to achieve.

    Thank you

  • Hello,

    So it looks like if (Vdc_pu1 > 410):

    • AQSFRC --> Load AQ sw force on CTR = 0 to force A and B low
    • DBCTL2 --> all writes/reads shadowed to load on CTR = 0
    • DBCTL --> don't invert A or B
    • DBRED/FED values = 1000
    • AQCTL --> use shadow mode and load on CTR = 0
    • AQCTLA/B --> clear PWMs low on AQs

    What count mode are you using and what are your original AQs? Are you using up-count?

    Can you try loading the shadow to active registers on CTR = PRD rather than CTR = 0?

    Best Regards,

    Allison

  • Hello,

    count mode is UPDOWN count mode. Initially (i.e before Vdc_pu1 >410 is true). EPWM4 is initialised as below

    EPwm4Regs.TBPRD = 1000;       // 1000 corresponds to 50kHz UPDOWN counter

    EPwm4Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0

    EPwm4Regs.TBCTR = 0x0000;                  // Clear counter

    // Setup counter mode

    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up and down

    EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading

    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT

    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;

     

    EPwm4Regs.TBCTL.bit.SYNCOSEL = 1;

    // Setup shadowing

    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero

    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    // Set actions

    EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;            // set PWM1A on event A, up

    EPwm4Regs.AQCTLA.bit.CAD = AQ_SET;          // clear PWM1A on event A,

    EPwm4Regs.AQCTLB.bit.CBU = AQ_SET;            // clear PWM1B on event B, up

    EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR;          // set PWM1B on event B

    // for deadband

    EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

    EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;

    EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;

    EPwm4Regs.DBRED.bit.DBRED = DB;

    EPwm4Regs.DBFED.bit.DBFED = DB;

    Based on the above initialization, which happens in main, I assume that AQCTL is not used in shadow mode. Only once the condition of Vdc_pu1 > 410 is true then the AQCTL shadow mode is activated.

    I used the shadow to active registers on CTR = PRD rather than CTR = 0, as below. But the result is same as shown in picture in my last comment.

    if(Vdc_pu1 > 410)

         {

             GpioDataRegs.GPASET.bit.GPIO2=1;

     

             EPwm4Regs.AQSFRC.bit.RLDCSF = 00;

             EPwm4Regs.AQCSFRC.bit.CSFA = 01;

             EPwm4Regs.AQCSFRC.bit.CSFB = 01;

             EPwm4Regs.DBCTL2.bit.SHDWDBCTLMODE = 01;

             EPwm4Regs.DBCTL2.bit.LOADDBCTLMODE = 00;

             EPwm4Regs.DBCTL.bit.POLSEL = 00;

             EPwm4Regs.DBRED.bit.DBRED = 1000;

             EPwm4Regs.DBFED.bit.DBFED = 1000;

             EPwm4Regs.AQCTL.bit.SHDWAQBMODE = 01;

             EPwm4Regs.AQCTL.bit.SHDWAQAMODE = 01;

             EPwm4Regs.AQCTL.bit.LDAQAMODE = 01;

             EPwm4Regs.AQCTL.bit.LDAQBMODE = 01;

             EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;           

             EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR;       

             EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;      

             EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR;

         }

    Thank you

  • Hello,

    It looks like the small pulse on channel EPWM4A and EPWM4B occurs on CTR = 0 when the loading is occurring, is that assumption correct? My question is do you have any other actions set to occur on counter =0? I'm trying to gauge why this could be occurring if you didn't have an AQ or trip output set to drive the PWM outputs high at 0.

    When you check the Vdc_pu1 variable, can you try only changing the action qualifiers so that all AQCTLA/AQCTLB register fields are set to "Clear" the EPWM channels low? (the default is to "do nothing"). For example, adding EPwm4Regs.AQCTLA.bit.ZRO = AQ_CLEAR;.

    Best Regards,

    Allison

  • Hello,

    "It looks like the small pulse on channel EPWM4A and EPWM4B occurs on CTR = 0 when the loading is occurring, is that assumption correct?"

    Answer = YES, a small pulse on EPWM4A and EPWM4B occurs on CTR = 0.

    "My question is do you have any other actions set to occur on counter =0?"

    Answer = Well, CMPA and CMPB are updated at CTR=0; other than that, no actions happen at CTR=0. 

    ADC acquisition starts at TBCTR(EPWM4) = TBPRD, and the

    ADCA module has 3 adc signal acquisition and ADCA(SOC0), ADCA(SOC1), and ADCA(SOC2) are used for the start of conversion,

    ADCB module has 3 adc signal acquisition and ADCB(SOC0), ADCB(SOC1), and ADCB(SOC2) are used for the start of conversion.

    ADCC module has 2 adc signal acquisition and ADCC(SOC0), ADCC(SOC1) are used for the start of conversion.

    ALL the ADC modules are triggered simultaneously at TBCTR(EPWM4) = TBPRD. So I assume SOC0 of ADCA, ADCB and ADCC acquire the samples simultaneously and at the EOC of ADCA(SOC2) an ISR is triggered in which the control algorithm for the PSFB converter runs.

    I have tried below things as suggested

    if(Vdc_pu1 > 410)

         {

             GpioDataRegs.GPASET.bit.GPIO2=1;

     

             EPwm4Regs.AQSFRC.bit.RLDCSF = 00;

             EPwm4Regs.AQCSFRC.bit.CSFA = 01;

             EPwm4Regs.AQCSFRC.bit.CSFB = 01;

             EPwm4Regs.DBRED.bit.DBRED = 1000;

             EPwm4Regs.DBFED.bit.DBFED = 1000;

             EPwm4Regs.DBCTL2.bit.SHDWDBCTLMODE = 01;

             EPwm4Regs.DBCTL2.bit.LOADDBCTLMODE = 00;

             EPwm4Regs.DBCTL.bit.POLSEL = 00;

             EPwm4Regs.AQCTL.bit.SHDWAQBMODE = 01;

             EPwm4Regs.AQCTL.bit.SHDWAQAMODE = 01;

             EPwm4Regs.AQCTL.bit.LDAQAMODE = 01;

             EPwm4Regs.AQCTL.bit.LDAQBMODE = 01;

             EPwm4Regs.AQCTLA.bit.ZRO = 01;

             EPwm4Regs.AQCTLB.bit.ZRO = 01;

    //         EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; // this line will not be executed           

    //         EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR; // this line will not be executed              

    //         EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; // this line will not be executed             

    //         EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR; // this line will not be executed        

         }

    and 2nd attempt as below

    if(Vdc_pu1 > 410)

         {

             GpioDataRegs.GPASET.bit.GPIO2=1;

     

             EPwm4Regs.AQSFRC.bit.RLDCSF = 00;

             EPwm4Regs.AQCSFRC.bit.CSFA = 01;

             EPwm4Regs.AQCSFRC.bit.CSFB = 01;

             EPwm4Regs.DBRED.bit.DBRED = 1000;

             EPwm4Regs.DBFED.bit.DBFED = 1000;

             EPwm4Regs.DBCTL2.bit.SHDWDBCTLMODE = 01;

             EPwm4Regs.DBCTL2.bit.LOADDBCTLMODE = 00;

             EPwm4Regs.DBCTL.bit.POLSEL = 00;

             EPwm4Regs.AQCTL.bit.SHDWAQBMODE = 01;

             EPwm4Regs.AQCTL.bit.SHDWAQAMODE = 01;

             EPwm4Regs.AQCTL.bit.LDAQAMODE = 01;

             EPwm4Regs.AQCTL.bit.LDAQBMODE = 01;

             EPwm4Regs.AQCTLA.bit.ZRO = 01;

             EPwm4Regs.AQCTLB.bit.ZRO = 01;

             EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;       

             EPwm4Regs.AQCTLA.bit.CAD = AQ_CLEAR; 

             EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;      

             EPwm4Regs.AQCTLB.bit.CBD = AQ_CLEAR;

         }

    But the waveform of EPWM4A and EPWM4B doesn't change at all and it shows a a glitch at TBCTR(EPWM4) = 0.

    I don't know why this thread says the issue is resolved. But I still have an issue. Do you want to open a new thread?