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TMS320F28375S: Timing concern on clearing the TZ FLAG then triggering next time TZ Trip through CMPSS

Johnny Chen
Expert 5330 points

Part Number: TMS320F28375S

Tool/software:

Hi Champ,

I am asking for my customer.

They attempt to use comparator and EPWM DCAEVT1 / DCAEVT2, to trigger TZISR in one-shot trip.

They plan to check the comparator output status and clear the TZ one-shot flag in another control flow (not in the TZISR, i.e. in a 10kHz Timer interrupt), checking the comparator output is low then clear the flag, then trigger the next time TZISR. 

(1). In above scenario, after user confirms that the comparator output is low, at the moment the comparator output just suddenly changes from low to High before user sets the command to clear the TZ FLAG. Is there a chance to cause that TZISR to be missed and not be executed in such condition ? Any consideration on the timing sequence here ?

(2). How does internal trip submodule mechanism to check whether the one-shot flag is cleared or not ? checking in every PWM clock cycle (EPWMCLK) ? It is believed it should affect the result of the first question.

(3). In TRM, it notes the condition to be latched, at least for a minimum of 3 ˟ TBCLK as below.

 (Figure 1)

It is not indicated the same thing specified in DS for Pulse duration for TZx input low, right ?

(Figure 2)

If not, where is the minimum of 3 ˟ TBCLK be latched specified in DS, or just a note in TRM ONLY ? Then, where is the min. Pulse duration be taken care of ?

(4). Confirming the estimation of complete execution time to reach out the first line of TZISR for an ePWM One-shot Trip Condition set through CMPSS, considering interrupt latency and wait states on the ISR or stack memories for additional latency. Would the expert explicitly list one by one separately ? estimated execution time from CMPSS -> EPWM-Xbar -> EPWM DC submodule -> TZISR (first line code). 

Thanks and regards,

Johnny

  • 0
    TI__Mastermind 27540 points

    Hi Johnny,

    Thanks for the inquiry. Let me double check on this information- I'll update and provide responses to your 3 questions tomorrow. Thanks!

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    TI__Expert 5330 points

    Hi Allison,

    Appreciate your support on the 3 questions.

    Adding one more question on the complete execution time from CMPSS to executing the first line code in TZISR. May come back later on this if you need more time to reconfirm with CMPSS & CPU subject expert.

    Thank you so much for the support.

    Regards,

    Johnny

  • 0 in reply to Johnny Chen
    TI__Mastermind 27540 points

    Hi Johnny,

    Sorry for the delay, but I will need another day to consult some other SMEs on this. Appreciate the patience!

    Best Regards,

    Allison

  • 0 in reply to Johnny Chen
    TI__Mastermind 27540 points

    Hi Johnny,

    I've reworded your questions a bit to ensure I understand what you are asking:

    (1) Customer uses comparator and EPWM DCAEVT1 / DCAEVT2, to trigger TZISR in OST trip. Is there any concern about the reaction time between the time when the user manually clears the TZ FLAG and the time when the next TZISR is triggered? Is there any case where the trip zone submodule would ignore the TZ FLAG if it is cleared right before a TXISR is triggered?

    For a one-shot trip interrupt sourced from the comparator, you need to be sure to clear the TZFLG and TZOSTFLG flags after the trip (comparator) condition is inactive, otherwise you can have an interrupt occur again without the flags being set (see TRM snippet below)

    What the customer could do here instead is use edge-triggered trip zone interrupts. There is an FAQ on how to do this. Please take a look and see if the customer would find it helpful to implement: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1413992/faq-c2000ware-how-to-configure-cmpss-and-epwm-for-edge-trigger-instead-of-level-trigger/5415065?tisearch=e2e-sitesearch&keymatch=CMPSS%252520rising#5415065 

    (2) How does internal trip submodule mechanism to check whether the one-shot flag is cleared or not? Is it checking every PWM clock cycle (EPWMCLK)?

    The flags are checked by the clock driving the EPWM module, so every EPWMCLK clock cycle.

    (3) In the TRM note, the trip signal must go low for at least for a minimum of 3 ˟ TBCLK in order to be latched. This timing is not specified in the DS for Pulse duration for TZx input low. Is this note only found in the TRM?

    The timing requirement in the TRM note is for different circumstances than the datasheet specification. The 3TBCLK note applies specifically to the Digital Compare submodule when using DCAEVT/DCBEVT as a Trip source. In this case, the 3TBCLK is needed to latch the condition properly. 

    The datasheet specification you sent is not specific to this condition, but a general guideline for direct trip source inputs (e.g. a GPIO used directly as a trip input source).

    (4) Is there an estimation on the execution time from CMPSS to the execution of the EPWM TZISR for a One-shot Trip (coming from CMPSS)? How can we consider interrupt latency and wait states on the ISR or stack memories for additional latency? Can we list the timings separately for each step from:    CMPSS -> EPWM-Xbar -> EPWM DC submodule -> TZISR (first line code).

    The timing of this depends on a number of different factors (e.g. code optimization and interrupt latency), but this can be measured by toggling a GPIO at the start of the interrupt and measuring the time between comparator going high/low and the GPIO toggle. Please also see this FAQ for interrupt latency: https://software-dl.ti.com/C2000/docs/c28x_interrupt_faq/html/index.html#ISR_Latency. 

    Best Regards,

    Allison