TMS320F280049C: TMS320F280049C : PLL configuration

Hello Prajaka,

The first configuration does not look correct. You have a multiplier of 40 and a divider of 3. The divider should be 4.

The third is also invalid - 100MHz is below the minimum VCO frequency for the PLL.

It looks like you're experiencing an error using the Flash plugin/loading code into Flash. You may need to go into the Flash plugin GUI (CCS Debug View > Tools > On-Chip Flash) and configure the PLL from there first, since you have a custom clock setup.

Best regards,
Ibukun

Hello Ibukun,

Thanks for your fast response.

PLL MUL = 0x28 and PLL DIV = 0x2 : in this configuration , clock is getting divided by 4 not 3.

I am referring the above table. Correct me if I am wrong.

Hello Prajakta,

Yes, you are correct. I thought you were referring to the PLL output divider (ODIV).

Did you try configuring the PLL first from the Flash plugin GUI as I mentioned?

Best regards,
Ibukun

Now I am using PLL configurations : PLL MUL = 0x28 and PLL DIV = 0x2.

With these values, code is getting flashed .. no error while flashing.

But I am facing another issue, When I flash the code first time, it runs smoothly.

As soon as do POR, code is getting stopped because of MCLKSTS  bit in MCDCR register is not getting clear. Its value remains 1.

What I understood from datasheet : OSCCLK detected missing, CLOCKFAILn Generated.

What could be the reason for this and how to get it resolved ??

Please support.

Hello Prajakta,

How did you initialize the crystal and clock? Did you use SysConfig, or did you write your own code? The error indeed indicates that the missing clock detection circuit has tripped. Please show your initialization function if possible.

Best regards,
Ibukun