TMS320F28377S: ADC sample

Hi Fengyu,

 What is the trigger from and what is ACQPS setting? 

You can sample the same pin simultaneously with multiple ADCs. However, you should take note of the following points:

• ADC conversions need to happen synchronously in order to maintain performance. This means that the prescale value (ADC clock divider) and the sample+hold time (ACQPS) must be identical on all the ADCs and respective SOCs in order to maintain synchronous operation. Multiple triggers may also be used, as long as the triggers are issued at the same time. Note that software triggers cannot be used to achieve synchronous conversion on this device, as they would not arrive simultaneously.
• Because the pin will be charging the S+H caps simultaneously, care must be taken to ensure that the ADC input network meets the settling time requirement, or that the ACQPS value is set accordingly. For further guidance on this, see the "Choosing an Acquisition Window Duration" topic in the TMS320F2837xS Real-Time Microcontrollers Technical Reference Manual (Rev. I) It is also recommended to use a high-bandwidth buffer on the VREFHI pin (if using external reference mode) to maximize ADC performance.

Hi Susmitha,

Thanks for your support. Customer will check the specific ACQPS and give us feedback. 

Besides, how much should the impedance between ADC pin to GND? Is it normal to have 30kohm differences between different ADC channels?

BR,

Fengyu

Hi Fengyu,

ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to VSSA.

How much is the difference between ADCINA0 channel compared to other channels?

Also, to achieve the data sheet spec minimum ACQPS, the source impedance needs to be ≤ 50Ω.

App note below comes with a simulation model for evaluating your input circuit design. 

ADC Input Circuit Evaluation for C2000 MCUs (using TINA-TI simulation tool) (Rev. A)

Thanks,

Susmitha