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TMS320F280039C: Interrupt response and GPIO flipping time.

Part Number: TMS320F280039C

Tool/software:

Hi experts,

I am testing the interrupt response time and GPIO flipping time on F280039C. I use interrupt upon CTR=CMPA to flip the GPIO and compare the timing of the rising edge the with the CMPA AQ pull-up. I found that the interval between CTR=CMPA and the GPIO set high is about 860 ns, and the GPIO flipping time is about 640 ns.

These two results is unexpected, since from the ACI benchmark, the interrupt response time should be 50 cycles, around 417ns for 120M CPU. In my case, it's 860-640 = 220 ns

Meanwhile, the GPIO flipping time of 640 ns seems a little bit long. Below is my code for the EPWM interrupt and the measured waveform (yellow: ePWM, blue, myGPIO1).

Any idea what am I missing here?

Regards,

Hang.

  • Hi Hang,

    The yellow waveform is EPWM configured to set on CMPA ?

    And you have ISR trigger on CMPA as well ?

    Why are you measuring GPIO rise and fall in ISR and comparing with interrupt latency benchmark ?

    What are measuring in the scope ?

    Maybe I didn't understand your question can you elaborate more

    Thanks.

  • Hi Bhatt,

    The Yellow is a AQ pull up at CMPA, using ePWM. The ISR is triggered on CMPA as well. In the ISR, I set the GPIO high, then toggle few times, as shown in the code.

    The interval between the first rising edge of blue and the rising edge of yellow should be interrupt latency + GPIO function latency. 

    The interval between the first rising edge and the first falling edge of the blue should be GPIO function latency only.

    I expect to measure the interrupt latency by subtracting the two intervals, and see if it matches with the document.

    Regards,

    Hang. 

  • Hi Hang,

    The interval between the first rising edge of blue and the rising edge of yellow should be interrupt latency + GPIO function latency. 

    The interval between the first rising edge and the first falling edge of the blue should be GPIO function latency only.

    These two are in two different time. How are you comparing blue pulse (gpio latency) with former.

    Also what is the document you are referring to ?

    Thanks

  • Hi Bhatt

    As the below image shows:

    Interval 1 = A (ISR latency)+ B (GPIO latency)

    Interval 2 = B

    I want A,, so I get A by A = interval1 - interval 2

    The document I referred to is spracw5a, you may find the ISR latency in Figure 2-3.

    Regards,

    Hang.

  • Hang,

    I see that you are subtracting B from the first A+B, but is B in both time intervals, same ?

    I also don't know what you mean by below : 
    AQ pull up at CMPA ?

    Yellow is a AQ pull up at CMPA, using ePWM

    Application note says : "The application uses a timer counter and a PWM counter to benchmark various parts of the application in cycle counts. As such, no external hardware like a scope is needed for measuring the benchmark results. The benchmark data is collected for each of the 1024 control loop execution iterations and output on the console window by printf messages in the application."

    Thanks.

  • Hi Bhatt,

    I am assuming B in both time intervals are the same, since they are same functions called with different parameter.

    I set the CTR=CMPA AQ event as "setting signal high", so that I can capture the CTR=CMPA timing by looking at the rising edge of the ePWM. I captured this timing because interrupt is triggered as this point. This timing is the begging of the "ISR latency". 

    I am measuring this using external hardware because my customer is verifying the results in the application note. they are using a different method to acquire this latency and expect it to match with the result acquired by timer counter.

    If the current method is somehow wrong, any idea how to measure this latency other than the method in the application note? 

    Regards,

    Hang.

  • Hang,

    B can be same in both interval, but do you know if B in first interval occurs after A and there is no delay or extra time in that interval.

    I am not aware of any other alternate method for this.

    Thanks

  • Hi Bhatt,

    Since GPIO flip is the first line in the ISR, and there is no other interrupt enabled, I think B is right after A. Is there anything that can possibly happens betwee A and B?

    Regards,

    Hang.