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TMS320F2800137: Timer frequency is not as expected, and changing the Timer base clock divider does not affect counter speed

Part Number: TMS320F2800137
Other Parts Discussed in Thread: C2000WARE

Tool/software:

I want to create a delay function. My idea is to create a counter with specified frequency and each time my delay function is called, it resets my counter value, and then wait till counter value reaches a calculated value.

To do that, I create a 10 MHz timer using EPWM, EPWM clock is 120 MHz and divide it by 12 (time base clock divider 1, high speed clock divider is 12).

I count the number of times my counter reaches 10000, and increase "i" value by 1 after each 1000 times.

I expect my "i" variable increased each 1 second, but it appears that "i" value increase faster, it is increased 12 times each second as I calculated.

Is something wrong with my config or my idea?

Another weird thing is that when I change time base clock divider to 128 

the increase speed of my i variable is not changed. But I followed instruction in C2000 EPWM.

Did I misunderstand how to calculate the speed of a counter?

Please let me know if anyone has a suggestion for my problem. Thanks for reading.

  • Hello Hai,

    From your screenshot, in this device TBCLK = SYSCLK so that setting seems fine.

    Few questions and some suggestions -->

    1. What c2000ware are you using for this?

    2. Also, could you please set a break point at the driverlib function that is supposed to set it with new clock dividers and check the following bits in register view window TBCTL.HSPCLKDIV and TBCTL.CLKDIV if they are updated correctly?

    Regards,

    Sumit