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TMS320F280039C: Having different CMPSS sets connect to same EPWM-Xbar

Johnny Chen
Expert 5310 points

Part Number: TMS320F280039C

Tool/software:

Hi Champ,

I am asking for my customer.

They are having two CMPSS sets (i.e. CMPSS1 & CMPSS2) output to connect to the same EPWM-XBAR (TRIP4) to EPWM DC-submodule then generate TZINT.

1). In TZINT, they will base on the condition on which CMPSS set outputs 1 (event may occur from CMPSS1 / CMPSS2 / CMPSS1&2) to do following corresponding procedure. Any register in CMPSS to poll, to know the event occurred from which CMPSS sets?

2). In DC-submodule, there is a DCTRIPSEL register to bring OR logic to ALL trip inputs to the EPWM, if all the trip inputs are coming from CMPSS sets, any ways to exactly know which CMPSS sets event occur ?

Thanks and regards,

Johnny 

  • 0
    TI__Mastermind 24521 points

    Hi Johnny,

    To find which CMPSS issued the trip, you can check the status register of the CMPSS modules with CMPSS_getStatus(). You can check the output status of the output or latched output depending on the configuration. If using the latched output, you can also clear the latch output from your control loop.

    Regards,

    Peter

  • 0 in reply to Peter Luong
    TI__Expert 5310 points

    Hi Peter,

    Thanks for the reply.

    I have noticed the COMPSTS Register for checking the the status of the CMPSS.

    1). From the bit COMPHSTS & COMPLSTS description from the register, it specifies for High/Low comparator digital filter output. Is the bit COMPHSTS also applicable to check the status if it is configured as "Asynchronous comparator output drives CTRIPH/L", not " Output of digital filter drives CTRIPH/L" in COMPCTL register ?

    From CMPSS Module Block Diagram, COMPHSTS should react to the output status from Synchronous comparator output drives.

    2). Then, is there any difference between selecting Asynchronous comparator output drives and Output of digital filter drives with configuring the digital filter SAMPWIN and THRESH to its min. value (SAMPWIN with 0 +1, THRESH with 0+1) ? Should be ONLY adding delays for Output of digital filter drives mentioned in Synchronizer, Digital Filter, and Latch Delays between these two configurations (Asynchronous/digital filter), right ?

    Thanks and regards,

    Johnny

  • +1 in reply to Johnny Chen
    TI__Mastermind 24521 points

    Hi Johnny,

    Thank you for your clarification, yes to use the COMPSTS register to indicate the output of the CMPSS, you have to use either the digital filter trip output or the latched version of the output. 

    1) Therefore, the status will not be visible when using either the ASYNC or SYNC outputs. You can reduce the cycle delay to the minimum which is the synchronizer adding 2 SYSCLK and the filter adding an additional 2 SYSCLK which is total of 4 SYSCLK. It should be that the digital filter output is same as SYNC output with additional filter delay, and SYNC output is just ASYNC output which is clocked to device clock edge

    Regards,

    Peter