Tool/software:
Dear Experts,
I got stuck at using TI's "Solar_CLA.h". We have successfully initialized CLA and ran simple task which was perfectly working. In the next step, I followed the steps provided in the Solar Library documentation (Solar Library) to perform clarke transformation.
#include "F28x_Project.h"
#include "math.h"
#include "Cla_Support.h"
#pragma DATA_SECTION(A,"CLADataLS0")
float A=5;
#pragma DATA_SECTION(B,"Cla1ToCpuMsgRAM")
float B;
interrupt void TimerOvf(void);
interrupt void PWM_Int(void);
interrupt void adcA_EOC(void);
interrupt void cla_isr(void);
void Initialize_GPIO(void);
void Initialize_PWM1(void);
void Custom_Init(void);
void timer0_init(void);
void Init_ADCs(void);
void InitCla(void);
int adc,pwm,b,cla=0;
float adc2,s,a0,a1,a2,a3,a4,a5,b2,b3,b4,b5,c2,c3,c4,c5=0;
int buff[500];
void main(void)
{
InitSysCtrl();
Custom_Init();
DINT;
Initialize_GPIO();
Initialize_PWM1();
Init_ADCs();
InitCla();
InitPieCtrl();
Cla1ForceTask8andWait();
IER = 0x0000;
IFR = 0x0000;
InitPieCtrl();
InitPieVectTable();
EALLOW;
PieCtrlRegs.PIEIER1.bit.INTx7 = 1; //Timer
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; //ADC-A1
PieCtrlRegs.PIEIER11.bit.INTx1 = 1; // Enable CLA Task1 in PIE group #11
PieVectTable.TIMER0_INT = &TimerOvf;
PieVectTable.ADCA1_INT = &adcA_EOC;
PieVectTable.CLA1_1_INT = &cla_isr;
PieCtrlRegs.PIECTRL.bit.ENPIE= 1;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
EDIS;
IER |= 1025;
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
timer0_init();
CpuTimer0Regs.TCR.bit.TSS=0;
while(1)
{
}
}
void Initialize_GPIO(void)
{
EALLOW;
GpioCtrlRegs.GPBDIR.bit.GPIO62 = 1;
GpioCtrlRegs.GPCDIR.bit.GPIO73= 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; //EPwm1
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; //SPIB CLK
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 2; //SPIB OUT
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 2; //SPIB IN ADC-1and 2 IN
GpioCtrlRegs.GPBDIR.bit.GPIO57 = 1;//CS-C
GpioCtrlRegs.GPBDIR.bit.GPIO58 = 1;//CS-B
GpioCtrlRegs.GPBDIR.bit.GPIO59 = 1;//CS-A
GpioDataRegs.GPBDAT.bit.GPIO57 =1;
GpioDataRegs.GPBDAT.bit.GPIO58 =1;
GpioDataRegs.GPBDAT.bit.GPIO59 =1;
GpioCtrlRegs.GPCMUX2.bit.GPIO93 = 0; //BUSY A
GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 0;// FIRST DATA A
EDIS;
}
void Custom_Init(void)
{
EALLOW;
ClkCfgRegs.AUXPLLMULT.bit.IMULT=20;
ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV=0;
ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1;
ClkCfgRegs.LOSPCP.bit.LSPCLKDIV = 2;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; ///source initsysctrl
CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
CpuSysRegs.PCLKCR13.bit.ADC_A = 1;
CpuSysRegs.PCLKCR0.bit.CLA1 = 1;
DevCfgRegs.CPUSEL0.bit.EPWM1 = 0;
EDIS;
}
void Initialize_PWM1(void)
{
EALLOW;
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm1Regs.TBPRD = 10000; // Set timer period
EPwm1Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // SYNC output on CTR = 0
// Setup shadow register load on ZERO
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0;
// Set Compare values
EPwm1Regs.CMPA.bit.CMPA = 10000/2; // Set compare A value
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO = 2; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAU = 1; // Clear PWM1A on event A, up count
//interrput enable
EPwm1Regs.ETSEL.bit.INTSEL = 1; //@ CTR = 0
EPwm1Regs.ETSEL.bit.INTEN = 1;
EPwm1Regs.ETPS.bit.INTPRD=1;
//SOCA to ADC
EPwm1Regs.ETSEL.bit.SOCAEN=1;
EPwm1Regs.ETSEL.bit.SOCASEL=1;
EPwm1Regs.ETPS.bit.SOCAPRD = 1;
EPwm1Regs.ETCLR.bit.SOCA = 1;
//EPWM4
EPwm4Regs.TBCTL.bit.CTRMODE = 0; // Count up
EPwm4Regs.TBPRD = 1000; // Set timer period
EPwm4Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm4Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = 0;
EPwm4Regs.TBCTL.bit.SYNCOSEL = 1; // SYNC output on CTR = 0
// Setup shadow register load on ZERO
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0;
EPwm4Regs.CMPCTL.bit.LOADAMODE = 0;
EPwm4Regs.CMPCTL.bit.LOADBMODE = 0;
// Set Compare values
EPwm4Regs.CMPA.bit.CMPA = 10000/2; // Set compare A value
// Set actions
EPwm4Regs.AQCTLA.bit.ZRO = 2; // Set PWM1A on Zero
EPwm4Regs.AQCTLA.bit.CAU = 1; // Clear PWM1A on event A, up count
//interrput enable
EPwm4Regs.ETSEL.bit.INTSEL = 1; //@ CTR = 0
EPwm4Regs.ETSEL.bit.INTEN = 1;
EPwm4Regs.ETPS.bit.INTPRD=1;
//SOCA to ADC
EPwm4Regs.ETSEL.bit.SOCAEN=1;
EPwm4Regs.ETSEL.bit.SOCASEL=1;
EPwm4Regs.ETPS.bit.SOCAPRD = 1;
EPwm4Regs.ETCLR.bit.SOCA = 1;
EDIS;
}
void timer0_init(void)
{
EALLOW;
CpuTimer0Regs.PRD.bit.LSW = 0x2D00;
CpuTimer0Regs.PRD.bit.MSW = 0x0131;
CpuTimer0Regs.TPR.bit.TDDR= 99;
CpuTimer0Regs.TCR.bit.TIE= 1;
CpuTimer0Regs.TCR.bit.TSS=1;
CpuTimer0Regs.TCR.bit.FREE=0;
CpuTimer0Regs.TCR.bit.TRB=0;
EDIS;
}
void Init_ADCs(void)
{
EALLOW;
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
DELAY_US(1000);
AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
AdcbRegs.ADCCTL2.bit.PRESCALE = 6;
AdccRegs.ADCCTL2.bit.PRESCALE = 6;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert pin A0
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; //SOC1 will convert pin A1
AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2; //SOC2 will convert pin A2
AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3; //SOC3 will convert pin A3
AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4; //SOC4 will convert pin A4
AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5; //SOC5 will convert pin A5
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert pin B2
AdcbRegs.ADCSOC1CTL.bit.CHSEL = 3; //SOC1 will convert pin B3
AdcbRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC2 will convert pin B4
AdcbRegs.ADCSOC3CTL.bit.CHSEL = 5; //SOC3 will convert pin B5
AdccRegs.ADCSOC0CTL.bit.CHSEL = 2; //SOC0 will convert pin C2
AdccRegs.ADCSOC1CTL.bit.CHSEL = 3; //SOC1 will convert pin C3
AdccRegs.ADCSOC2CTL.bit.CHSEL = 4; //SOC2 will convert pin C4
AdccRegs.ADCSOC3CTL.bit.CHSEL = 5; //SOC3 will convert pin C5
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC4CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC5CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC0CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC1CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC2CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC3CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCBURSTCTL.bit.BURSTEN = 1;
AdcaRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
AdcaRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
AdcbRegs.ADCBURSTCTL.bit.BURSTEN = 1;
AdcbRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
AdcbRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
AdccRegs.ADCBURSTCTL.bit.BURSTEN = 1;
AdccRegs.ADCBURSTCTL.bit.BURSTSIZE = 5;
AdccRegs.ADCBURSTCTL.bit.BURSTTRIGSEL =5;
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
//for another trigger to run CLA to estimate theta
AdcaRegs.ADCSOC6CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC7CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC8CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC4CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC5CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcbRegs.ADCSOC6CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC4CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC5CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdccRegs.ADCSOC6CTL.bit.ACQPS = 14; //sample window is 100 SYSCLK cycles
AdcaRegs.ADCSOC6CTL.bit.TRIGSEL= 11; //ePWM4
AdcaRegs.ADCSOC7CTL.bit.TRIGSEL= 11; //ePWM4
AdcaRegs.ADCSOC8CTL.bit.TRIGSEL= 11; //ePWM4
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 8; //EOC6
//how to configure another ADCA ISR as only one ISR is available????
EDIS;
}
void InitCla(void)
{
// extern uint32_t Cla1funcsRunStart, Cla1funcsLoadStart, Cla1funcsLoadSize;
EALLOW;
//--- Memory Configuration - Master CPU and CLA Select
MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1; // 0=CPU 1=CPU and CLA
MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1; // 0=CPU 1=CPU and CLA
MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 1; // 0=CPU 1=CPU and CLA
MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 0; // 0=CPU 1=CPU and CLA
MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1; // 0=CPU 1=CPU and CLA
MemCfgRegs.LSxMSEL.bit.MSEL_LS5 = 0; // 0=CPU 1=CPU and CLA
//--- Memory Configuration - CLA Data Memory and CLA Program Memory Select
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0; // 0=CLA data memory 1=CLA program memory
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0; // 0=CLA data memory 1=CLA program memory
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 0; // 0=CLA data memory 1=CLA program memory
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 0; // 0=CLA data memory 1=CLA program memory
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1; // 0=CLA data memory 1=CLA program memory
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS5 = 0; // 0=CLA data memory 1=CLA program memory
//--- Initialize CLA task interrupt vectors
// On Type-1 CLAs the MVECT registers accept full 16-bit task addresses as
// opposed to offsets used on older Type-0 CLAs.
Cla1Regs.MVECT1 = (uint16_t)(&Cla1Task1);
Cla1Regs.MVECT2 = (uint16_t)(&Cla1Task2);
Cla1Regs.MVECT3 = (uint16_t)(&Cla1Task3);
Cla1Regs.MVECT4 = (uint16_t)(&Cla1Task4);
Cla1Regs.MVECT5 = (uint16_t)(&Cla1Task5);
Cla1Regs.MVECT6 = (uint16_t)(&Cla1Task6);
Cla1Regs.MVECT7 = (uint16_t)(&Cla1Task7);
Cla1Regs.MVECT8 = (uint16_t)(&Cla1Task8);
//--- Select Task interrupt source /******** TRIGGER SOURCE FOR EACH TASK (unlisted numbers are reserved) ********/
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1 = 0; // 0=none 8=ADCBINT3 16=ADCDINT1 32=XINT4 42=EPWM7INT 70=TINT2 78=ECAP4INT 95=SD1INT 114=SPIRXINTC
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK2 = 0; // 1=ADCAINT1 9=ADCBINT4 17=ADCDINT2 33=XINT5 43=EPWM8INT 71=MXEVTA 79=ECAP5INT 96=SD2INT
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK3 = 0; // 2=ADCAINT2 10=ADCBEVT 18=ADCDINT3 36=EPWM1INT 44=EPWM9INT 72=MREVTA 80=ECAP6INT 107=UPP1INT
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK4 = 0; // 3=ADCAINT3 11=ADCCINT1 19=ADCDINT4 37=EPWM2INT 45=EPWM10INT 73=MXEVTB 83=EQEP1INT 109=SPITXINTA
DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK5 = 0; // 4=ADCAINT4 12=ADCCINT2 20=ADCDEVT 38=EPWM3INT 46=EPWM11INT 74=MREVTB 84=EQEP2INT 110=SPIRXINTA
DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK6 = 0; // 5=ADCAEVT 13=ADCCINT3 29=XINT1 39=EPWM4INT 47=EPWM12INT 75=ECAP1INT 85=EQEP3INT 111=SPITXINTB
DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK7 = 0; // 6=ADCBINT1 14=ADCCINT4 30=XINT2 40=EPWM5INT 48=TINT0 76=ECAP2INT 87=HRCAP1INT 112=SPIRXINTB
DmaClaSrcSelRegs.CLA1TASKSRCSEL2.bit.TASK8 = 0; // 7=ADCBINT2 15=ADCCEVT 31=XINT3 41=EPWM6INT 69=TINT1 77=ECAP3INT 88=HRCAP2INT 113=SPITXINTC
DmaClaSrcSelRegs.CLA1TASKSRCSEL1.bit.TASK1 = 1; //ADCAINT1
//--- CLA1TASKSRCSELx register lock control
DmaClaSrcSelRegs.CLA1TASKSRCSELLOCK.bit.CLA1TASKSRCSEL1 = 0; // Write a 1 to lock (cannot be cleared once set)
DmaClaSrcSelRegs.CLA1TASKSRCSELLOCK.bit.CLA1TASKSRCSEL2 = 0; // Write a 1 to lock (cannot be cleared once set)
//--- Enable use software to start a task (IACK)
Cla1Regs.MCTL.bit.IACKE = 1; // Enable IACKE to start task using software
//--- Force one-time initialization Task 8 - zero delay buffer
Cla1Regs.MIER.all = 0x0001; // Enable CLA interrupt 1
// asm(" IACK #0x0001"); // IACK - CLA task force instruction
// asm(" RPT #3 || NOP"); // Wait at least 4 cycles
// while(Cla1Regs.MIRUN.bit.INT1 == 1); // Loop until task completes
//--- Enable CLA task interrupts
EDIS;
} // end of InitCla()
void TimerOvf(void)
{
EPwm1Regs.ETFRC.bit.SOCA = 1;
b= b+1;
if(b>10)
{
b=0;
}
GpioDataRegs.GPBTOGGLE.bit.GPIO62=1;
CpuTimer0Regs.TCR.bit.TIF = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
void adcA_EOC(void)
{
adc=adc+1;
adc2=adc*0.5;
s=sin(adc2);
buff[adc] = s;
if(adc>100)
{
adc=0;
}
a0 = AdcaResultRegs.ADCRESULT0; //Va
a1 = AdcaResultRegs.ADCRESULT1; //Vb
a2 = AdcaResultRegs.ADCRESULT2; //Vc
a3 = AdcaResultRegs.ADCRESULT3; //Vdc
a4 = AdcaResultRegs.ADCRESULT4;
a5 = AdcaResultRegs.ADCRESULT5;
b2 = AdcbResultRegs.ADCRESULT0; //Ia
b3 = AdcbResultRegs.ADCRESULT1; //Ib
b4 = AdcbResultRegs.ADCRESULT2; //Ic
b5 = AdcbResultRegs.ADCRESULT3; //Idc
c2 = AdccResultRegs.ADCRESULT0; //Vrg
c3 = AdccResultRegs.ADCRESULT1; //Vyg
c4 = AdccResultRegs.ADCRESULT2; //Vbg
c5 = AdccResultRegs.ADCRESULT3;
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
//CLA ISR
void cla_isr(void)
{
cla=cla+1;
if(cla>10)
{
cla = 0;
}
PieCtrlRegs.PIEACK.all = PIEACK_GROUP11;
}
#include "F28x_Project.h"
#include "math.h"
#include "Cla_Support.h"
#pragma DATA_SECTION(clarke1, "Cla1ToCpuMsgRAM");
ClaToCpu_Volatile CLARKE_CLA clarke1;
//task 1
interrupt void Cla1Task1 (void)
{
float Vmeas_a,Vmeas_b,Vmeas_c;
Vmeas_a =AdcaResultRegs.ADCRESULT0;
Vmeas_b =AdcaResultRegs.ADCRESULT1;
Vmeas_c =AdcaResultRegs.ADCRESULT2;
clarke1.a= Vmeas_a;
clarke1.b= Vmeas_b;
clarke1.c= Vmeas_c;
CLARKE_CLA_MACRO(clarke1);
}
interrupt void Cla1Task2 (void)
{
}
interrupt void Cla1Task3 (void)
{
}
interrupt void Cla1Task4 (void)
{
}
interrupt void Cla1Task5 (void)
{
}
interrupt void Cla1Task6 (void)
{
}
interrupt void Cla1Task7 (void)
{
}
interrupt void Cla1Task8 (void)
{
// Local Variables
CLARKE_CLA_init(clarke1);
}
//--- end of file -----------------------------------------------------
/*
* Cla_Support.h
*
* Created on: 08-Oct-2024
* Author: RAJESH
*/
#ifndef INCLUDES_CLA_SUPPORT_H_
#define INCLUDES_CLA_SUPPORT_H_
#include "F2837xD_Device.h"
#include "F2837xD_Cla_defines.h"
#include <stdint.h>
#include "Solar_CLA.h"
extern ClaToCpu_Volatile CLARKE_CLA clarke1;
#ifdef __cplusplus
extern "C" {
#endif
//
// Globals
//
/*
extern float32 A;
extern float32 B;
extern Uint16 C;
*/
interrupt void Cla1Task1();
interrupt void Cla1Task2();
interrupt void Cla1Task3();
interrupt void Cla1Task4();
interrupt void Cla1Task5();
interrupt void Cla1Task6();
interrupt void Cla1Task7();
interrupt void Cla1Task8();
#ifdef __cplusplus
}
#endif // extern "C"
#endif /* INCLUDES_CLA_SUPPORT_H_ */
CCS threw several errors. The above are three files of the project. one, main.c and other two clatasks and its .h file. The complete project is also attached for the reference.
ERRORS: Description Resource Path Location Type #102 "CLARKE_CLA" has already been declared in the current scope Cla_Support.h #20 identifier "clarke1" is undefined cla.c #20 identifier "clarke1" is undefined cla.c #20 identifier "ClaToCpu_Volatile" is undefined Cla_Support.h #20 identifier "ClaToCpu_Volatile" is undefined cla.c #66 expected a ";" Cla_Support.h #66 expected a ";" cla.c gmake: *** [cla.obj] Error 1 gmake: *** [main.obj] Error 1 gmake: Target 'all' not remade because of errors.
If you want this variable to be allocated to the Cla1ToCpuMsgRAM, you will need to initialize it globally from your main C file with the DATA_SECTION pragma. You can add the extern for this into your Cla_Support.h shared header file.