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TMS320F28377D: Requirement for connection with ET1100

Shengyue Zhong
Intellectual 1150 points
Part Number: TMS320F28377D

Tool/software:

Hi Team,

I have two questions about connection with ET1100, could you please help to clarify? Thanks.

1. ET1100 is connected to TI's 28377 via the EMIF port. Can the ET1100 be accessed in 100ns cycles if the busy signal is enabled? Or do I need to meet write cycles greater than 280 ns for the timing to be safe?

2. The busy signal goes to the Xwait signal of the DSP, but it does not pass through the FPGA, with about 10 ns of delay. Is there any adjustment needed on the timing sequence design? 

  • 0
    TI__Guru**** 192126 points

    Hi Shengyue,

    Are you connecting ET1100 to CS0 as a synchronous memory or to CS[4:2] as an asynchronous memory? 

    If ET1100 is used as an async memory, the write cycle time is determined by settings of the w_setup, w_strobe and w_hold which define the setup time, strobe time and hold time for the data pins. 

    1. The write access length must satisfy the memory (ET1100) minimum Write Cycle Time

    2. The W_STROBE must be set to satisfy the memory (ET1100) nCE pulse width constraint

    Refer to the AC characteristics for a write access in ET1100 datasheet to determine the appropriate settings for these parameters.

  • 0 in reply to QJ Wang
    TI__Intellectual 1150 points

    Hi QJ,

    Thanks for your information. I set it as an asynchronous memory. Below is my configuration, hope that get some comments from you.

  • 0 in reply to Shengyue Zhong
    TI__Guru**** 192126 points

    Hi Shengyue,

    I don't see any problem in the waveforms.