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LAUNCHXL-F28379D: C2000 microcontrollers forum

Sweta Pal
Prodigy 80 points
Part Number: LAUNCHXL-F28379D
Other Parts Discussed in Thread: C2000WARE

Tool/software:

For dual core, I am facing memory over-writing issue for some buffers. I am using USB in Core1 and ADC, Timer0 and Timer1 in Core2. 

After flashing both projects, USB, ADC and timers are working fine . But I am facing issue of over writing data in some buffers in Core2. When I try to change the linker file, I got trap.

I have provided the information below, Please check the linkers and let me know which point I am missing due to which some buffers of Core2 are getting over-written.

in CCS properties, I am giving below configuration for Core1 project

Core 1 Linker file is as below:


MEMORY
{
PAGE 0 : /* Program Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
/* BEGIN is used for the "boot to Flash" bootloader mode */

BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x000123, length = 0x0002DD

RAMLS0 : origin = 0x008000, length = 0x000800
RAMD1 : origin = 0x00B800, length = 0x000800

/* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

RESET : origin = 0x3FFFC0, length = 0x000002

/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */

FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
TEXT_SECTION : origin = 0x090000, length = 0x028000
// FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
// FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
// FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
// FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
//FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
//FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
// FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */

PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
SYSMEM_SECTION : origin = 0x010000 , length = 0x002000
//RAMLS3 : origin = 0x009800, length = 0x000800
//RAMLS4 : origin = 0x00A000, length = 0x001000
//RAMLS5 : origin = 0x00A800, length = 0x000800
RAMD0 : origin = 0x00B000, length = 0x000800
RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
RAMGS3 : origin = 0x00F000, length = 0x001000
//RAMGS4 : origin = 0x010000, length = 0x001000
//RAMGS5 : origin = 0x011000, length = 0x001000
RAMGS6 : origin = 0x012000, length = 0x001000
RAMGS7 : origin = 0x013000, length = 0x001000
RAMGS8 : origin = 0x014000, length = 0x001000
RAMGS9 : origin = 0x015000, length = 0x001000
RAMGS10 : origin = 0x016000, length = 0x001000

RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x000FF8

// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */

// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}

SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB, PAGE = 0, ALIGN(8)
.text : > TEXT_SECTION, PAGE = 0, ALIGN(8)
codestart : > BEGIN, PAGE = 0, ALIGN(8)
/* Allocate uninitalized data sections: */
.stack : > RAMM1, PAGE = 1
//.heap : > HEAP_SECTION, PAGE = 1
.switch : > FLASHB PAGE = 0, ALIGN(8)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

#if defined(__TI_EABI__)
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
.bss : > RAMGS1, PAGE = 1
.bss:output : > RAMD1, PAGE = 0
.bss:cio : > RAMGS1, PAGE = 1
.data : > RAMGS6, PAGE = 1
.sysmem : > SYSMEM_SECTION, PAGE = 1
/* Initalized sections go in Flash */
.const : > FLASHE, PAGE = 0, ALIGN(8)
#else
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
.ebss : >> RAMD0 | RAMGS0 | RAMGS1, PAGE = 1
.esysmem : > RAMD0, PAGE = 1
.cio : > RAMD0, PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASHE PAGE = 0, ALIGN(8)
#endif

Filter_RegsFile : > RAMGS0, PAGE = 1

SHARERAMGS0 : > RAMGS0, PAGE = 1
SHARERAMGS1 : > RAMGS1, PAGE = 1
SHARERAMGS2 : > RAMGS2, PAGE = 1
ramgs0 : > RAMGS0, PAGE = 1
ramgs1 : > RAMGS1, PAGE = 1

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#else
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif

#endif

/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}

GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}

/* The following section definition are for SDFM examples */
Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
Filter4_RegsFile : > RAMGS9, PAGE = 1, fill=0x4444
Difference_RegsFile : >RAMGS10, PAGE = 1, fill=0x3333
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

in CCS properties, I am giving below configuration for Core2 project:

Core 2 Linker file is as below:


MEMORY
{
PAGE 0 :
/* BEGIN is used for the "boot to SARAM" bootloader mode */

BEGIN : origin = 0x080000, length = 0x000002
RAMM0 : origin = 0x0000A2, length = 0x00035E
RAMD0 : origin = 0x00B000, length = 0x000800
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

RESET : origin = 0x3FFFC0, length = 0x000002

/* Flash sectors */
FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
FLASHB : origin = 0x082000, length = 0x004000 /* on-chip Flash */
// FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */
FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */

// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 :

BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */
RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */
// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
RAMD1 : origin = 0x00B800, length = 0x000800
STACK_MEM : origin = 0x008800, length = 0x001000 /*RAMLS1 to RAMLS5 */
RAMLS5 : origin = 0x00A800, length = 0x000800

RAMGS0 : origin = 0x00C000, length = 0x001000
RAMGS1 : origin = 0x00D000, length = 0x001000
RAMGS2 : origin = 0x00E000, length = 0x001000
CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
}

SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHB PAGE = 0, ALIGN(8)
.text : > FLASHB PAGE = 0, ALIGN(8)
codestart : > BEGIN PAGE = 0, ALIGN(8)

/* Allocate uninitalized data sections: */
.stack : > STACK_MEM PAGE = 1

/* Initalized sections go in Flash */
.switch : > FLASHB PAGE = 0, ALIGN(8)
.reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

#if defined(__TI_EABI__)
.init_array : > FLASHB, PAGE = 0, ALIGN(8)
.bss : > RAMLS5, PAGE = 1
.bss:output : > RAMLS3, PAGE = 0
.bss:cio : > RAMLS5, PAGE = 1
.data : > RAMLS5, PAGE = 1
.sysmem : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.const : > FLASHF, PAGE = 0, ALIGN(8)
#else
.pinit : > FLASHB, PAGE = 0, ALIGN(8)
.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
.esysmem : > RAMLS5, PAGE = 1
.cio : > RAMLS5, PAGE = 1
/* Initalized sections go in Flash */
.econst : >> FLASHF PAGE = 0, ALIGN(8)
#endif

SHARERAMGS0 : > RAMGS0, PAGE = 1
SHARERAMGS1 : > RAMGS1, PAGE = 1
SHARERAMGS2 : > RAMGS2, PAGE = 1

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#else
.TI.ramfunc : {} LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#else
ramfuncs : LOAD = FLASHD,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
PAGE = 0, ALIGN(8)
#endif
#endif

/* The following section definitions are required when using the IPC API Drivers */
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}

GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

  • 0
    Prodigy 80 points

    Please suggest me solution ASAP as my work is blocked.

  • 0 in reply to Sweta Pal
    TI__Expert 8631 points

    Hi Sweta,

    In the cpu2 linker cmd, i find LSRAM (LS0-4) already defined in page 0 and STACK_MEM defined with LSRAM address in page 1, this will create a conflict.

    Please update the STACK_MEM location to use RAMM1 location.

    Please find the sample linker cmd file (RAM and FLASH) in the SDK in the C2000Ware\device_support\f2837xd\common\cmd folder.

    I will go through the files in detail, but please try updating this section and try again.

    Thanks

    Aswin

  • 0 in reply to Aswin P
    Prodigy 80 points

    Hi,

    Thanks for your suggestion. I tried with one, but it did not work for me. 

    After that I checked the flash linke examples and according to that I modify my linkers. After that out of 9 buffers, 6 buffers are working finr(not over writing) but still remaining buffers have the problem. I am not able to understand. Please check the below linkers:

    CPU1 linker:


    MEMORY
    {
    PAGE 0 : /* Program Memory */
    /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
    /* BEGIN is used for the "boot to Flash" bootloader mode */

    BEGIN : origin = 0x080000, length = 0x000002
    RAMM0 : origin = 0x000123, length = 0x0002DD
    RAMD0 : origin = 0x00B000, length = 0x000800
    RAMLS0 : origin = 0x008000, length = 0x000400
    // RAMLS1 : origin = 0x008800, length = 0x000800
    //RAMLS2 : origin = 0x009000, length = 0x000800
    //RAMLS3 : origin = 0x009800, length = 0x000800

    RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

    // RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

    RESET : origin = 0x3FFFC0, length = 0x000002

    /* Flash sectors */
    FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
    FLASHB : origin = 0x082000, length = 0x001000 /* on-chip Flash */
    FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
    FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
    FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
    FLASHF : origin = 0x090000, length = 0x001000 /* on-chip Flash */
    FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
    FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
    FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
    FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
    FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
    FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
    FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
    FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */

    // FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

    PAGE 1 : /* Data Memory */
    /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

    BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */
    RAMM1 : origin = 0x000400, length = 0x000300 /* on-chip RAM block M1 */
    // RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
    // RAMD1 : origin = 0x00B800, length = 0x000800
    STACK_MEM : origin = 0x008800, length = 0x000100
    RAMLS4 : origin = 0x00A000, length = 0x000800
    //RAMLS5 : origin = 0x00A800, length = 0x000800

    RAMGS0 : origin = 0x00C000, length = 0x001000
    RAMGS1 : origin = 0x00D000, length = 0x001000
    RAMGS2 : origin = 0x00E000, length = 0x001000

    // RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */

    // RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

    RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

    CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
    CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
    }

    SECTIONS
    {
    /* Allocate program areas: */
    .cinit : > FLASHB PAGE = 0, ALIGN(8)
    .text : >> FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8)
    codestart : > BEGIN PAGE = 0, ALIGN(8)
    /* Allocate uninitalized data sections: */
    .stack : > RAMM1 PAGE = 1
    .switch : > FLASHB PAGE = 0, ALIGN(8)
    .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

    #if defined(__TI_EABI__)
    .init_array : > FLASHB, PAGE = 0, ALIGN(8)
    .bss : > RAMLS4, PAGE = 1
    .bss:output : > RAMLS4, PAGE = 0
    .bss:cio : > RAMLS4, PAGE = 1
    .data : > RAMLS4, PAGE = 1
    .sysmem : > RAMLS4, PAGE = 1
    /* Initalized sections go in Flash */
    .const : > FLASHF, PAGE = 0, ALIGN(8)

    #else
    .pinit : > FLASHB, PAGE = 0, ALIGN(8)
    .ebss : >> RAMLS4 | RAMGS0 | RAMGS1, PAGE = 1
    .esysmem : > RAMLS4, PAGE = 1
    .cio : > RAMLS4, PAGE = 1
    /* Initalized sections go in Flash */
    .econst : >> FLASHF PAGE = 0, ALIGN(8)
    #endif

    Filter_RegsFile : > RAMGS0, PAGE = 1

    SHARERAMGS0 : > RAMGS0, PAGE = 1
    SHARERAMGS1 : > RAMGS1, PAGE = 1
    SHARERAMGS2 : > RAMGS2, PAGE = 1
    ramgs0 : > RAMGS0, PAGE = 1
    ramgs1 : > RAMGS1, PAGE = 1
    MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, PAGE = 1
    MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, PAGE = 1

    #ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
    #if defined(__TI_EABI__)
    .TI.ramfunc : {} LOAD = FLASHD,
    RUN = RAMLS0,
    LOAD_START(RamfuncsLoadStart),
    LOAD_SIZE(RamfuncsLoadSize),
    LOAD_END(RamfuncsLoadEnd),
    RUN_START(RamfuncsRunStart),
    RUN_SIZE(RamfuncsRunSize),
    RUN_END(RamfuncsRunEnd),
    PAGE = 0, ALIGN(8)
    #else
    .TI.ramfunc : {} LOAD = FLASHD,
    RUN = RAMLS0,
    LOAD_START(_RamfuncsLoadStart),
    LOAD_SIZE(_RamfuncsLoadSize),
    LOAD_END(_RamfuncsLoadEnd),
    RUN_START(_RamfuncsRunStart),
    RUN_SIZE(_RamfuncsRunSize),
    RUN_END(_RamfuncsRunEnd),
    PAGE = 0, ALIGN(8)
    #endif
    #else
    ramfuncs : LOAD = FLASHD,
    RUN = RAMLS0,
    LOAD_START(_RamfuncsLoadStart),
    LOAD_SIZE(_RamfuncsLoadSize),
    LOAD_END(_RamfuncsLoadEnd),
    RUN_START(_RamfuncsRunStart),
    RUN_SIZE(_RamfuncsRunSize),
    RUN_END(_RamfuncsRunEnd),
    PAGE = 0, ALIGN(8)
    #endif

    #endif

    /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
    PUTBUFFER
    PUTWRITEIDX
    GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
    GETBUFFER : TYPE = DSECT
    GETWRITEIDX : TYPE = DSECT
    PUTREADIDX : TYPE = DSECT
    }

    /* The following section definition are for SDFM examples */
    Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111
    Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222
    // Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333
    // Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444
    // Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333
    }

    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */

    CPU2 Linker:


    MEMORY
    {
    PAGE 0 :
    /* BEGIN is used for the "boot to SARAM" bootloader mode */

    BEGIN : origin = 0x080000, length = 0x000002
    RAMM0 : origin = 0x0000A2, length = 0x00035E
    RAMD0 : origin = 0x00B000, length = 0x000800
    RAMLS0 : origin = 0x008400, length = 0x000400
    // RAMLS1 : origin = 0x008800, length = 0x000800
    // RAMLS2 : origin = 0x009000, length = 0x000800
    // RAMLS3 : origin = 0x009800, length = 0x000800

    RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
    RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

    // RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

    RESET : origin = 0x3FFFC0, length = 0x000002

    /* Flash sectors */
    FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */
    FLASHB : origin = 0x083000, length = 0x001000 /* on-chip Flash */
    //FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */
    //FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */
    //FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */
    FLASHF : origin = 0x091000, length = 0x007000 /* on-chip Flash */
    FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */
    FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */
    FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */
    FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */
    FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */
    FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */
    FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */
    FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */

    // FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

    PAGE 1 :

    BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */
    RAMM1 : origin = 0x000700, length = 0x0000F8 /* on-chip RAM block M1 */
    RAMD1 : origin = 0x00B800, length = 0x000800

    STACK_MEM : origin = 0x008900, length = 0x000100
    STACK_SIZE : origin = 0x008A00, length = 0x000E00
    RAMLS5 : origin = 0x00A800, length = 0x000800
    //RAMLS4 : origin = 0x00A000, length = 0x000800
    //RAMGS0 : origin = 0x00C000, length = 0x001000

    RAMGS3 : origin = 0x00F000, length = 0x001000
    RAMGS4 : origin = 0x010000, length = 0x001000
    RAMGS5 : origin = 0x011000, length = 0x001000
    RAMGS6 : origin = 0x012000, length = 0x001000
    RAMGS7 : origin = 0x013000, length = 0x001000
    RAMGS8 : origin = 0x014000, length = 0x001000
    RAMGS9 : origin = 0x015000, length = 0x001000
    RAMGS10 : origin = 0x016000, length = 0x001000
    CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400
    CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400
    }

    SECTIONS
    {
    /* Allocate program areas: */
    .cinit : > FLASHB PAGE = 0, ALIGN(8)
    .text : > FLASHF | FLASHG | FLASHH PAGE = 0, ALIGN(8)
    codestart : > BEGIN PAGE = 0, ALIGN(8)

    /* Allocate uninitalized data sections: */
    .stack : > STACK_SIZE PAGE = 1

    /* Initalized sections go in Flash */
    .switch : > FLASHB PAGE = 0, ALIGN(8)
    .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */

    #if defined(__TI_EABI__)
    .init_array : > FLASHB, PAGE = 0, ALIGN(8)
    .bss : > RAMLS5, PAGE = 1
    .bss:output : > RAMLS0, PAGE = 0
    .bss:cio : > RAMLS5, PAGE = 1
    .data : > STACK_MEM, PAGE = 1
    .sysmem : > RAMLS5, PAGE = 1
    /* Initalized sections go in Flash */
    .const : > FLASHF, PAGE = 0, ALIGN(8)
    #else
    .pinit : > FLASHB, PAGE = 0, ALIGN(8)
    //.ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1
    .esysmem : > RAMLS5, PAGE = 1
    .cio : > RAMLS5, PAGE = 1
    /* Initalized sections go in Flash */
    .econst : >> FLASHF PAGE = 0, ALIGN(8)
    #endif

    SHARERAMGS0 : > RAMGS5, PAGE = 1
    SHARERAMGS1 : > RAMGS6, PAGE = 1
    SHARERAMGS2 : > RAMGS7, PAGE = 1
    MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, PAGE = 1
    MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, PAGE = 1
    #ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
    #if defined(__TI_EABI__)
    .TI.ramfunc : {} LOAD = FLASHG,
    RUN = RAMLS0,
    LOAD_START(RamfuncsLoadStart),
    LOAD_SIZE(RamfuncsLoadSize),
    LOAD_END(RamfuncsLoadEnd),
    RUN_START(RamfuncsRunStart),
    RUN_SIZE(RamfuncsRunSize),
    RUN_END(RamfuncsRunEnd),
    PAGE = 0, ALIGN(8)
    #else
    .TI.ramfunc : {} LOAD = FLASHG,
    RUN = RAMLS0,
    LOAD_START(_RamfuncsLoadStart),
    LOAD_SIZE(_RamfuncsLoadSize),
    LOAD_END(_RamfuncsLoadEnd),
    RUN_START(_RamfuncsRunStart),
    RUN_SIZE(_RamfuncsRunSize),
    RUN_END(_RamfuncsRunEnd),
    PAGE = 0, ALIGN(8)
    #endif
    #else
    ramfuncs : LOAD = FLASHG,
    RUN = RAMLS0,
    LOAD_START(_RamfuncsLoadStart),
    LOAD_SIZE(_RamfuncsLoadSize),
    LOAD_END(_RamfuncsLoadEnd),
    RUN_START(_RamfuncsRunStart),
    RUN_SIZE(_RamfuncsRunSize),
    RUN_END(_RamfuncsRunEnd),
    PAGE = 0, ALIGN(8)
    #endif
    #endif

    /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
    PUTBUFFER
    PUTWRITEIDX
    GETREADIDX
    }

    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
    GETBUFFER : TYPE = DSECT
    GETWRITEIDX : TYPE = DSECT
    PUTREADIDX : TYPE = DSECT
    }
    }

    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */

    Could you please check and suggest?

  • 0 in reply to Sweta Pal
    Prodigy 80 points

    Please suggest, why still some buffers are overlapping?

  • 0 in reply to Sweta Pal
    TI__Mastermind 32655 points

    Hi Sweta Pal,

    Aswin is out of office. I had a look at the linker cmd files you shared.

    Please note that the GSRAMs are shared across CPU1 and CPU2. Each of the block needs to be allocated to one of the CPUs. Can you make sure you dont use the same GSRAM on both the CPU linker cmd files. If you have any shared memory, you may keep them in both linker cmd files, but make sure it is initialized only from one CPU. In case of EABI, compiler inserts code to zero initialize all the uninitialized sections and one CPU may overwrite the values written by other CPU. To disable auto-init, you may use type=NOINIT. Eg:

    ramgs0 : > RAMGS0, type=NOINIT

    Regards,

    Veena