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TMS320F280039C: What is the specific description of the D2 (Down 2) algorithm in pbist ?

Hengchen Tian
Prodigy 150 points

Part Number: TMS320F280039C
Other Parts Discussed in Thread: C2000WARE

Tool/software:


File path:C:\ti\c2000\C2000Ware_5_01_00_00\libraries\boot_rom\f28003x\rev0\rom_sources\F28003x_ROM\bootROM\include\cpu1brom_pbist.h


Note: The D2 (Down 2) algorithm appears here, so ask if there is a documentation for this algorithm.


In the C2000Tm Memory Power-On Self-Test (M-POST) document, you can only see the March13n algorithm, there is no description of the D2 algorithm.

  • 0
    Prodigy 130 points

    I have the same problem！

  • 0 in reply to ?? ?
    TI__Guru* 86220 points

    While March13n is a static memory fault test(CPU speed or RAM access time for this test is not the main care-about), the Down2 test is exercising both the address/data bus timings, as well as the overall speed of the RAM itself to present data back to the busses in a timely manner. 

    To compare it to the details of March13n in that app note; the Down2 algo does a one time write to the memory under test, and then reads back the data with the goal of changing as many address/data lines on back to back reads as possible.

    The name Down2 is purely an internal TI name, and not something that has industry wide naming like the March13n

    I'll see what I can do to get the documentation updated.

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Prodigy 130 points

    Thank you. Your reply is of great help to me. Please let me know if you will update relevant documents in the future.

  • 0 in reply to MatthewPate
    Prodigy 150 points

    It helps a lot,

    Much appreciate

    Best,

    Hengchen